drivers: serial: sam0: Implement DMA async API
This adds support for the async API for SAM0 SERCOM USARTs using DMA to drive the device. Tested on SAMD21 with a few trivial programs and with tests/drivers/uart/uart_async_api. Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This commit is contained in:
Derek Hageman
Anas Nashif
parent
64e02021ee
commit
55bb37e35c
3 changed files with 702 additions and 4 deletions
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@ -9,5 +9,6 @@ menuconfig UART_SAM0
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depends on SOC_FAMILY_SAM0
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select DMA if UART_ASYNC_API
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help
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This option enables the SERCOMx USART driver for Atmel SAM0 MCUs.
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@ -10,6 +10,7 @@
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#include <misc/__assert.h>
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#include <soc.h>
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#include <uart.h>
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#include <dma.h>
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/* Device constant configuration parameters */
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struct uart_sam0_dev_cfg {
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@ -18,9 +19,15 @@ struct uart_sam0_dev_cfg {
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u32_t pads;
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u32_t pm_apbcmask;
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u16_t gclk_clkctrl_id;
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#if CONFIG_UART_INTERRUPT_DRIVEN
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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void (*irq_config_func)(struct device *dev);
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#endif
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#if CONFIG_UART_ASYNC_API
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u8_t tx_dma_request;
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u8_t tx_dma_channel;
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u8_t rx_dma_request;
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u8_t rx_dma_channel;
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#endif
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};
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/* Device run time data */
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@ -29,6 +36,29 @@ struct uart_sam0_dev_data {
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uart_irq_callback_user_data_t cb;
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void *cb_data;
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#endif
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#if CONFIG_UART_ASYNC_API
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const struct uart_sam0_dev_cfg *cfg;
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struct device *dma;
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uart_callback_t async_cb;
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void *async_cb_data;
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struct k_delayed_work tx_timeout_work;
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const u8_t *tx_buf;
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size_t tx_len;
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struct k_delayed_work rx_timeout_work;
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size_t rx_timeout_time;
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size_t rx_timeout_chunk;
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u32_t rx_timeout_start;
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u8_t *rx_buf;
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size_t rx_len;
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size_t rx_processed_len;
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u8_t *rx_next_buf;
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size_t rx_next_len;
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bool rx_waiting_for_irq;
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bool rx_timeout_from_isr;
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#endif
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};
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#define DEV_CFG(dev) \
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@ -71,6 +101,272 @@ static int uart_sam0_set_baudrate(SercomUsart *const usart, u32_t baudrate,
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return 0;
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}
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#if CONFIG_UART_ASYNC_API
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static void uart_sam0_dma_tx_done(void *arg, u32_t id, int error_code)
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{
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ARG_UNUSED(id);
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ARG_UNUSED(error_code);
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struct device *dev = arg;
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struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
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k_delayed_work_cancel(&dev_data->tx_timeout_work);
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int key = irq_lock();
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struct uart_event evt = {
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.type = UART_TX_DONE,
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.data.tx = {
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.buf = dev_data->tx_buf,
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.len = dev_data->tx_len,
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},
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};
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dev_data->tx_buf = NULL;
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dev_data->tx_len = 0U;
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if (evt.data.tx.len != 0U && dev_data->async_cb) {
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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irq_unlock(key);
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}
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static int uart_sam0_tx_halt(struct uart_sam0_dev_data *dev_data)
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{
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const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
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int key = irq_lock();
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size_t tx_active = dev_data->tx_len;
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struct dma_status st;
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struct uart_event evt = {
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.type = UART_TX_ABORTED,
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.data.tx = {
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.buf = dev_data->tx_buf,
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.len = 0U,
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},
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};
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dev_data->tx_buf = NULL;
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dev_data->tx_len = 0U;
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dma_stop(dev_data->dma, cfg->tx_dma_channel);
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irq_unlock(key);
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if (dma_get_status(dev_data->dma, cfg->tx_dma_channel, &st) == 0) {
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evt.data.tx.len = tx_active - st.pending_length;
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}
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if (tx_active) {
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if (dev_data->async_cb) {
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static void uart_sam0_tx_timeout(struct k_work *work)
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{
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struct uart_sam0_dev_data *dev_data = CONTAINER_OF(work,
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struct uart_sam0_dev_data, tx_timeout_work);
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uart_sam0_tx_halt(dev_data);
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}
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static void uart_sam0_notify_rx_processed(struct uart_sam0_dev_data *dev_data,
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size_t processed)
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{
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if (!dev_data->async_cb) {
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return;
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}
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if (dev_data->rx_processed_len == processed) {
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return;
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}
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struct uart_event evt = {
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.type = UART_RX_RDY,
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.data.rx = {
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.buf = dev_data->rx_buf,
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.offset = dev_data->rx_processed_len,
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.len = processed - dev_data->rx_processed_len,
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},
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};
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dev_data->rx_processed_len = processed;
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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static void uart_sam0_dma_rx_done(void *arg, u32_t id, int error_code)
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{
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ARG_UNUSED(id);
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ARG_UNUSED(error_code);
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struct device *dev = arg;
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struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
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const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
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SercomUsart * const regs = cfg->regs;
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int key = irq_lock();
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if (dev_data->rx_len == 0U) {
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irq_unlock(key);
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return;
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}
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uart_sam0_notify_rx_processed(dev_data, dev_data->rx_len);
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if (dev_data->async_cb) {
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struct uart_event evt = {
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.type = UART_RX_BUF_RELEASED,
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.data.rx_buf = {
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.buf = dev_data->rx_buf,
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},
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};
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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/* No next buffer, so end the transfer */
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if (!dev_data->rx_next_len) {
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dev_data->rx_buf = NULL;
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dev_data->rx_len = 0U;
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if (dev_data->async_cb) {
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struct uart_event evt = {
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.type = UART_RX_DISABLED,
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};
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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irq_unlock(key);
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return;
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}
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dev_data->rx_buf = dev_data->rx_next_buf;
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dev_data->rx_len = dev_data->rx_next_len;
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dev_data->rx_next_buf = NULL;
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dev_data->rx_next_len = 0U;
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dev_data->rx_processed_len = 0U;
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dma_reload(dev_data->dma, cfg->rx_dma_channel,
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(u32_t)(&(regs->DATA.reg)),
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(u32_t)dev_data->rx_buf, dev_data->rx_len);
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/*
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* If there should be a timeout, handle starting the DMA in the
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* ISR, since reception resets it and DMA completion implies
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* reception. This also catches the case of DMA completion during
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* timeout handling.
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*/
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if (dev_data->rx_timeout_time != K_FOREVER) {
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dev_data->rx_waiting_for_irq = true;
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regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
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irq_unlock(key);
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return;
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}
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/* Otherwise, start the transfer immediately. */
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dma_start(dev_data->dma, cfg->rx_dma_channel);
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struct uart_event evt = {
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.type = UART_RX_BUF_REQUEST,
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};
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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irq_unlock(key);
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}
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static void uart_sam0_rx_timeout(struct k_work *work)
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{
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struct uart_sam0_dev_data *dev_data = CONTAINER_OF(work,
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struct uart_sam0_dev_data, rx_timeout_work);
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const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
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SercomUsart * const regs = cfg->regs;
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struct dma_status st;
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int key = irq_lock();
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if (dev_data->rx_len == 0U) {
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irq_unlock(key);
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return;
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}
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/*
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* Stop the DMA transfer and restart the interrupt read
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* component (so the timeout restarts if there's still data).
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* However, just ignore it if the transfer has completed (nothing
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* pending) that means the DMA ISR is already pending, so just let
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* it handle things instead when we re-enable IRQs.
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*/
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dma_stop(dev_data->dma, cfg->rx_dma_channel);
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if (dma_get_status(dev_data->dma, cfg->rx_dma_channel,
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&st) == 0 && st.pending_length == 0U) {
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irq_unlock(key);
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return;
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}
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u8_t *rx_dma_start = dev_data->rx_buf + dev_data->rx_len -
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st.pending_length;
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size_t rx_processed = rx_dma_start - dev_data->rx_buf;
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/*
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* We know we still have space, since the above will catch the
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* empty buffer, so always restart the transfer.
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*/
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dma_reload(dev_data->dma, cfg->rx_dma_channel,
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(u32_t)(&(regs->DATA.reg)),
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(u32_t)rx_dma_start,
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dev_data->rx_len - rx_processed);
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dev_data->rx_waiting_for_irq = true;
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regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
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/*
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* Never do a notify on a timeout started from the ISR: timing
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* granularity means the first timeout can be in the middle
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* of reception but still have the total elapsed time exhausted.
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* So we require a timeout chunk with no data seen at all
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* (i.e. no ISR entry).
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*/
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if (dev_data->rx_timeout_from_isr) {
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dev_data->rx_timeout_from_isr = false;
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k_delayed_work_submit(&dev_data->rx_timeout_work,
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dev_data->rx_timeout_chunk);
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irq_unlock(key);
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return;
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}
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u32_t now = k_uptime_get_32();
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u32_t elapsed = now - dev_data->rx_timeout_start;
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if (elapsed >= dev_data->rx_timeout_time) {
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/*
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* No time left, so call the handler, and let the ISR
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* restart the timeout when it sees data.
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*/
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uart_sam0_notify_rx_processed(dev_data, rx_processed);
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} else {
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/*
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* Still have time left, so start another timeout.
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*/
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u32_t remaining = MIN(dev_data->rx_timeout_time - elapsed,
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dev_data->rx_timeout_chunk);
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k_delayed_work_submit(&dev_data->rx_timeout_work, remaining);
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}
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irq_unlock(key);
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}
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#endif
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static int uart_sam0_init(struct device *dev)
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{
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int retval;
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@ -112,10 +408,78 @@ static int uart_sam0_init(struct device *dev)
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return retval;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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cfg->irq_config_func(dev);
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
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dev_data->cfg = cfg;
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dev_data->dma = device_get_binding(CONFIG_DMA_0_NAME);
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k_delayed_work_init(&dev_data->tx_timeout_work, uart_sam0_tx_timeout);
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k_delayed_work_init(&dev_data->rx_timeout_work, uart_sam0_rx_timeout);
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if (cfg->tx_dma_channel != 0xFFU) {
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struct dma_config dma_cfg = { 0 };
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struct dma_block_config dma_blk = { 0 };
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if (!dev_data->dma) {
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return -ENOTSUP;
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}
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dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
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dma_cfg.source_data_size = 1;
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dma_cfg.dest_data_size = 1;
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dma_cfg.callback_arg = dev;
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dma_cfg.dma_callback = uart_sam0_dma_tx_done;
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dma_cfg.block_count = 1;
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dma_cfg.head_block = &dma_blk;
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dma_cfg.dma_slot = cfg->tx_dma_request;
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dma_blk.block_size = 1;
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dma_blk.dest_address = (u32_t)(&(usart->DATA.reg));
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dma_blk.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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retval = dma_config(dev_data->dma, cfg->tx_dma_channel,
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&dma_cfg);
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if (retval != 0) {
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return retval;
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}
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}
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if (cfg->rx_dma_channel != 0xFFU) {
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struct dma_config dma_cfg = { 0 };
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struct dma_block_config dma_blk = { 0 };
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if (!dev_data->dma) {
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return -ENOTSUP;
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}
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dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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dma_cfg.source_data_size = 1;
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dma_cfg.dest_data_size = 1;
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dma_cfg.callback_arg = dev;
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dma_cfg.dma_callback = uart_sam0_dma_rx_done;
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dma_cfg.block_count = 1;
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dma_cfg.head_block = &dma_blk;
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dma_cfg.dma_slot = cfg->rx_dma_request;
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dma_blk.block_size = 1;
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dma_blk.source_address = (u32_t)(&(usart->DATA.reg));
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dma_blk.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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retval = dma_config(dev_data->dma, cfg->rx_dma_channel,
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&dma_cfg);
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if (retval != 0) {
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return retval;
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}
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}
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#endif
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usart->CTRLA.bit.ENABLE = 1;
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wait_synchronization(usart);
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@ -145,18 +509,58 @@ static void uart_sam0_poll_out(struct device *dev, unsigned char c)
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usart->DATA.reg = c;
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}
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#if CONFIG_UART_INTERRUPT_DRIVEN
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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static void uart_sam0_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
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#if CONFIG_UART_INTERRUPT_DRIVEN
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if (dev_data->cb) {
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dev_data->cb(dev_data->cb_data);
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}
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#endif
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#if CONFIG_UART_ASYNC_API
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const struct uart_sam0_dev_cfg *const cfg = DEV_CFG(dev);
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SercomUsart * const regs = cfg->regs;
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if (dev_data->rx_len && regs->INTFLAG.bit.RXC &&
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dev_data->rx_waiting_for_irq) {
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dev_data->rx_waiting_for_irq = false;
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regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
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/* Receive started, so request the next buffer */
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if (dev_data->rx_next_len == 0U && dev_data->async_cb) {
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struct uart_event evt = {
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.type = UART_RX_BUF_REQUEST,
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};
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dev_data->async_cb(&evt, dev_data->async_cb_data);
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}
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/*
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* If we have a timeout, restart the time remaining whenever
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* we see data.
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*/
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if (dev_data->rx_timeout_time != K_FOREVER) {
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dev_data->rx_timeout_from_isr = true;
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dev_data->rx_timeout_start = k_uptime_get_32();
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k_delayed_work_submit(&dev_data->rx_timeout_work,
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dev_data->rx_timeout_chunk);
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}
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/* DMA will read the currently ready byte out */
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dma_start(dev_data->dma, cfg->rx_dma_channel);
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}
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||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if CONFIG_UART_INTERRUPT_DRIVEN
|
||||
|
||||
static int uart_sam0_fifo_fill(struct device *dev, const u8_t *tx_data, int len)
|
||||
{
|
||||
SercomUsart *regs = DEV_CFG(dev)->regs;
|
||||
|
|
@ -249,6 +653,231 @@ static void uart_sam0_irq_callback_set(struct device *dev,
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
|
||||
static int uart_sam0_callback_set(struct device *dev, uart_callback_t callback,
|
||||
void *user_data)
|
||||
{
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
|
||||
dev_data->async_cb = callback;
|
||||
dev_data->async_cb_data = user_data;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uart_sam0_tx(struct device *dev, const u8_t *buf, size_t len,
|
||||
u32_t timeout)
|
||||
{
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
const struct uart_sam0_dev_cfg *const cfg = DEV_CFG(dev);
|
||||
SercomUsart *regs = DEV_CFG(dev)->regs;
|
||||
int retval;
|
||||
|
||||
if (!dev_data->dma || cfg->tx_dma_channel == 0xFFU) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
if (len > 0xFFFFU) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int key = irq_lock();
|
||||
|
||||
if (dev_data->tx_len != 0U) {
|
||||
retval = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
dev_data->tx_buf = buf;
|
||||
dev_data->tx_len = len;
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
retval = dma_reload(dev_data->dma, cfg->tx_dma_channel, (u32_t)buf,
|
||||
(u32_t)(&(regs->DATA.reg)), len);
|
||||
if (retval != 0U) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
if (timeout != K_FOREVER) {
|
||||
k_delayed_work_submit(&dev_data->tx_timeout_work, timeout);
|
||||
}
|
||||
|
||||
return dma_start(dev_data->dma, cfg->tx_dma_channel);
|
||||
err:
|
||||
irq_unlock(key);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int uart_sam0_tx_abort(struct device *dev)
|
||||
{
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
const struct uart_sam0_dev_cfg *const cfg = DEV_CFG(dev);
|
||||
|
||||
if (!dev_data->dma || cfg->tx_dma_channel == 0xFFU) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
k_delayed_work_cancel(&dev_data->tx_timeout_work);
|
||||
|
||||
return uart_sam0_tx_halt(dev_data);
|
||||
}
|
||||
|
||||
static int uart_sam0_rx_enable(struct device *dev, u8_t *buf, size_t len,
|
||||
u32_t timeout)
|
||||
{
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
const struct uart_sam0_dev_cfg *const cfg = DEV_CFG(dev);
|
||||
SercomUsart *regs = DEV_CFG(dev)->regs;
|
||||
int retval;
|
||||
|
||||
if (!dev_data->dma || cfg->rx_dma_channel == 0xFFU) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
if (len > 0xFFFFU) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int key = irq_lock();
|
||||
|
||||
if (dev_data->rx_len != 0U) {
|
||||
retval = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Read off anything that was already there */
|
||||
while (regs->INTFLAG.bit.RXC) {
|
||||
char discard = regs->DATA.reg;
|
||||
|
||||
(void)discard;
|
||||
}
|
||||
|
||||
retval = dma_reload(dev_data->dma, cfg->rx_dma_channel,
|
||||
(u32_t)(&(regs->DATA.reg)),
|
||||
(u32_t)buf, len);
|
||||
if (retval != 0) {
|
||||
return retval;
|
||||
}
|
||||
|
||||
dev_data->rx_buf = buf;
|
||||
dev_data->rx_len = len;
|
||||
dev_data->rx_processed_len = 0U;
|
||||
dev_data->rx_waiting_for_irq = true;
|
||||
dev_data->rx_timeout_from_isr = true;
|
||||
dev_data->rx_timeout_time = timeout;
|
||||
dev_data->rx_timeout_chunk = MAX(timeout / 4U, 1);
|
||||
|
||||
regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
|
||||
|
||||
irq_unlock(key);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
irq_unlock(key);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int uart_sam0_rx_buf_rsp(struct device *dev, u8_t *buf, size_t len)
|
||||
{
|
||||
if (len > 0xFFFFU) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
int key = irq_lock();
|
||||
int retval = 0;
|
||||
|
||||
if (dev_data->rx_len == 0U) {
|
||||
retval = -EACCES;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (dev_data->rx_next_len != 0U) {
|
||||
retval = -EBUSY;
|
||||
goto err;
|
||||
}
|
||||
|
||||
dev_data->rx_next_buf = buf;
|
||||
dev_data->rx_next_len = len;
|
||||
|
||||
irq_unlock(key);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
irq_unlock(key);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int uart_sam0_rx_disable(struct device *dev)
|
||||
{
|
||||
struct uart_sam0_dev_data *const dev_data = DEV_DATA(dev);
|
||||
const struct uart_sam0_dev_cfg *const cfg = DEV_CFG(dev);
|
||||
SercomUsart *const regs = cfg->regs;
|
||||
struct dma_status st;
|
||||
|
||||
k_delayed_work_cancel(&dev_data->rx_timeout_work);
|
||||
|
||||
int key = irq_lock();
|
||||
|
||||
if (dev_data->rx_len == 0U) {
|
||||
irq_unlock(key);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
|
||||
dma_stop(dev_data->dma, cfg->rx_dma_channel);
|
||||
|
||||
if (dev_data->rx_next_len) {
|
||||
struct uart_event evt = {
|
||||
.type = UART_RX_BUF_RELEASED,
|
||||
.data.rx_buf = {
|
||||
.buf = dev_data->rx_next_buf,
|
||||
},
|
||||
};
|
||||
|
||||
dev_data->rx_next_buf = NULL;
|
||||
dev_data->rx_next_len = 0U;
|
||||
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->async_cb(&evt, dev_data->async_cb_data);
|
||||
}
|
||||
}
|
||||
|
||||
if (dma_get_status(dev_data->dma, cfg->rx_dma_channel,
|
||||
&st) == 0 && st.pending_length != 0U) {
|
||||
size_t rx_processed = dev_data->rx_len - st.pending_length;
|
||||
|
||||
uart_sam0_notify_rx_processed(dev_data, rx_processed);
|
||||
}
|
||||
|
||||
struct uart_event evt = {
|
||||
.type = UART_RX_BUF_RELEASED,
|
||||
.data.rx_buf = {
|
||||
.buf = dev_data->rx_buf,
|
||||
},
|
||||
};
|
||||
|
||||
dev_data->rx_buf = NULL;
|
||||
dev_data->rx_len = 0U;
|
||||
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->async_cb(&evt, dev_data->async_cb_data);
|
||||
}
|
||||
|
||||
evt.type = UART_RX_DISABLED;
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->async_cb(&evt, dev_data->async_cb_data);
|
||||
}
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static const struct uart_driver_api uart_sam0_driver_api = {
|
||||
.poll_in = uart_sam0_poll_in,
|
||||
.poll_out = uart_sam0_poll_out,
|
||||
|
|
@ -265,9 +894,17 @@ static const struct uart_driver_api uart_sam0_driver_api = {
|
|||
.irq_update = uart_sam0_irq_update,
|
||||
.irq_callback_set = uart_sam0_irq_callback_set,
|
||||
#endif
|
||||
#if CONFIG_UART_ASYNC_API
|
||||
.callback_set = uart_sam0_callback_set,
|
||||
.tx = uart_sam0_tx,
|
||||
.tx_abort = uart_sam0_tx_abort,
|
||||
.rx_enable = uart_sam0_rx_enable,
|
||||
.rx_buf_rsp = uart_sam0_rx_buf_rsp,
|
||||
.rx_disable = uart_sam0_rx_disable,
|
||||
#endif
|
||||
};
|
||||
|
||||
#if CONFIG_UART_INTERRUPT_DRIVEN
|
||||
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
|
||||
#define UART_SAM0_IRQ_HANDLER_DECL(n) \
|
||||
static void uart_sam0_irq_config_##n(struct device *dev)
|
||||
#define UART_SAM0_IRQ_HANDLER_FUNC(n) \
|
||||
|
|
@ -287,6 +924,53 @@ static void uart_sam0_irq_config_##n(struct device *dev) \
|
|||
#define UART_SAM0_IRQ_HANDLER(n)
|
||||
#endif
|
||||
|
||||
#if CONFIG_UART_ASYNC_API
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA 0xFFU
|
||||
#endif
|
||||
#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA
|
||||
#define DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA 0xFFU
|
||||
#endif
|
||||
|
||||
#define UART_SAM0_DMA_CHANNELS(n) \
|
||||
.tx_dma_request = SERCOM##n##_DMAC_ID_TX, \
|
||||
.tx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_TXDMA, \
|
||||
.rx_dma_request = SERCOM##n##_DMAC_ID_RX, \
|
||||
.rx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_RXDMA
|
||||
#else
|
||||
#define UART_SAM0_DMA_CHANNELS(n)
|
||||
#endif
|
||||
|
||||
#define UART_SAM0_SERCOM_PADS(n) \
|
||||
(DT_ATMEL_SAM0_UART_SERCOM_##n##_RXPO << SERCOM_USART_CTRLA_RXPO_Pos) |\
|
||||
(DT_ATMEL_SAM0_UART_SERCOM_##n##_TXPO << SERCOM_USART_CTRLA_TXPO_Pos)
|
||||
|
|
@ -299,6 +983,7 @@ static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
|
|||
.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \
|
||||
.pads = UART_SAM0_SERCOM_PADS(n), \
|
||||
UART_SAM0_IRQ_HANDLER_FUNC(n) \
|
||||
UART_SAM0_DMA_CHANNELS(n) \
|
||||
}
|
||||
|
||||
#define UART_SAM0_DEVICE_INIT(n) \
|
||||
|
|
|
|||
|
|
@ -35,4 +35,16 @@ properties:
|
|||
category: required
|
||||
description: Transmit Data Pinout
|
||||
generation: define
|
||||
|
||||
rxdma:
|
||||
type: int
|
||||
category: optional
|
||||
description: Receive DMA channel
|
||||
generation: define
|
||||
|
||||
txdma:
|
||||
type: int
|
||||
category: optional
|
||||
description: Transmit DMA channel
|
||||
generation: define
|
||||
...
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue