drivers: ipm: add driver based on stm32 hsem
Some STM32 SOC, like stm32h745 and stm32h747 doesn't have IPCC. Provide a STM32 HSEM based ipm driver for these SOC. Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
This commit is contained in:
HaiLong Yang
Carles Cufí
parent
9a80196e28
commit
559e1269e7
3 changed files with 229 additions and 0 deletions
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@ -9,5 +9,6 @@ zephyr_library_sources_ifdef(CONFIG_IPM_STM32_IPCC ipm_stm32_ipcc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_NRFX ipm_nrfx_ipc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_CAVS_IDC ipm_cavs_idc.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_INTEL_ADSP ipm_intel_adsp.c)
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zephyr_library_sources_ifdef(CONFIG_IPM_STM32_HSEM ipm_stm32_hsem.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE ipm_handlers.c)
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@ -112,6 +112,20 @@ config IPM_INTEL_ADSP
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help
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Driver for the Host-DSP Mailbox Communication channel.
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config IPM_STM32_HSEM
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bool "STM32 HSEM controller"
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depends on STM32H7_DUAL_CORE
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help
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Driver for stm32 HSEM mailbox
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config IPM_STM32_HSEM_CPU
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int "HSEM CPU ID"
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default 1
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range 1 2
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depends on IPM_STM32_HSEM
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help
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use to define the CPU ID used by HSEM
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module = IPM
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module-str = ipm
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source "subsys/logging/Kconfig.template.log_config"
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214
drivers/ipm/ipm_stm32_hsem.c
Normal file
214
drivers/ipm/ipm_stm32_hsem.c
Normal file
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@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_hsem_mailbox
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#include <device.h>
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#include <drivers/clock_control.h>
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#include <drivers/ipm.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "stm32_hsem.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(ipm_stm32_hsem, CONFIG_IPM_LOG_LEVEL);
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#define HSEM_CPU1 1
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#define HSEM_CPU2 2
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#if CONFIG_IPM_STM32_HSEM_CPU == HSEM_CPU1
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#define ll_hsem_enableit_cier LL_HSEM_EnableIT_C1IER
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#define ll_hsem_disableit_cier LL_HSEM_DisableIT_C1IER
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#define ll_hsem_clearflag_cicr LL_HSEM_ClearFlag_C1ICR
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#define ll_hsem_isactiveflag_cmisr LL_HSEM_IsActiveFlag_C1MISR
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#else /* HSEM_CPU2 */
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#define ll_hsem_enableit_cier LL_HSEM_EnableIT_C2IER
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#define ll_hsem_disableit_cier LL_HSEM_DisableIT_C2IER
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#define ll_hsem_clearflag_cicr LL_HSEM_ClearFlag_C2ICR
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#define ll_hsem_isactiveflag_cmisr LL_HSEM_IsActiveFlag_C2MISR
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#endif /* CONFIG_IPM_STM32_HSEM_CPU */
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struct stm32_hsem_mailbox_config {
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void (*irq_config_func)(const struct device *dev);
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struct stm32_pclken pclken;
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};
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struct stm32_hsem_mailbox_data {
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uint32_t tx_semid;
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uint32_t rx_semid;
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ipm_callback_t callback;
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void *user_data;
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};
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static struct stm32_hsem_mailbox_data stm32_hsem_mailbox_0_data;
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void stm32_hsem_mailbox_ipm_rx_isr(const struct device *dev)
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{
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struct stm32_hsem_mailbox_data *data = dev->data;
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uint32_t mask_semid = (1U << data->rx_semid);
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/* Check semaphore rx_semid interrupt status */
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if (!ll_hsem_isactiveflag_cmisr(HSEM, mask_semid))
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return;
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/* Notify user with NULL data pointer */
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if (data->callback) {
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data->callback(dev, data->user_data, 0, NULL);
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}
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/* Clear semaphore rx_semid interrupt status and masked status */
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ll_hsem_clearflag_cicr(HSEM, mask_semid);
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}
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static void stm32_hsem_mailbox_irq_config_func(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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stm32_hsem_mailbox_ipm_rx_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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int stm32_hsem_mailbox_ipm_send(const struct device *dev, int wait, uint32_t id,
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const void *buff, int size)
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{
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struct stm32_hsem_mailbox_data *data = dev->data;
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ARG_UNUSED(wait);
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ARG_UNUSED(buff);
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if (size) {
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LOG_WRN("stm32 HSEM not support data transfer");
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return -EMSGSIZE;
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}
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if (id) {
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LOG_WRN("stm32 HSEM only support a single instance of mailbox");
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return -EINVAL;
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}
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/* Lock the semaphore tx_semid */
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z_stm32_hsem_lock(data->tx_semid, HSEM_LOCK_DEFAULT_RETRY);
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/**
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* Release the semaphore tx_semid.
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* This will trigger a HSEMx interrupt on another CPU.
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*/
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z_stm32_hsem_unlock(data->tx_semid);
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return 0;
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}
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void stm32_hsem_mailbox_ipm_register_callback(const struct device *dev,
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ipm_callback_t cb,
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void *user_data)
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{
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struct stm32_hsem_mailbox_data *data = dev->data;
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data->callback = cb;
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data->user_data = user_data;
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}
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int stm32_hsem_mailbox_ipm_max_data_size_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* stm32 HSEM not support data transfer */
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return 0;
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}
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uint32_t stm32_hsem_mailbox_ipm_max_id_val_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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/* stm32 HSEM only support a single instance of mailbox */
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return 0;
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}
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int stm32_hsem_mailbox_ipm_set_enabled(const struct device *dev, int enable)
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{
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struct stm32_hsem_mailbox_data *data = dev->data;
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uint32_t mask_semid = (1U << data->rx_semid);
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if (enable) {
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/* Clear semaphore rx_semid interrupt status and masked status */
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ll_hsem_clearflag_cicr(HSEM, mask_semid);
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/* Enable semaphore rx_semid on HESMx interrupt */
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ll_hsem_enableit_cier(HSEM, mask_semid);
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} else {
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/* Disable semaphore rx_semid on HSEMx interrupt */
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ll_hsem_disableit_cier(HSEM, mask_semid);
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}
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return 0;
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}
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static int stm32_hsem_mailbox_init(const struct device *dev)
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{
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struct stm32_hsem_mailbox_data *data = dev->data;
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const struct stm32_hsem_mailbox_config *cfg = dev->config;
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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/* Config transfer semaphore */
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switch (CONFIG_IPM_STM32_HSEM_CPU) {
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case HSEM_CPU1:
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/* Enable clock */
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if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
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LOG_WRN("Failed to enable clock");
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return -EIO;
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}
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data->tx_semid = CFG_HW_IPM_CPU2_SEMID;
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data->rx_semid = CFG_HW_IPM_CPU1_SEMID;
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break;
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case HSEM_CPU2:
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data->tx_semid = CFG_HW_IPM_CPU1_SEMID;
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data->rx_semid = CFG_HW_IPM_CPU2_SEMID;
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break;
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}
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cfg->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api stm32_hsem_mailbox_ipm_dirver_api = {
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.send = stm32_hsem_mailbox_ipm_send,
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.register_callback = stm32_hsem_mailbox_ipm_register_callback,
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.max_data_size_get = stm32_hsem_mailbox_ipm_max_data_size_get,
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.max_id_val_get = stm32_hsem_mailbox_ipm_max_id_val_get,
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.set_enabled = stm32_hsem_mailbox_ipm_set_enabled,
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};
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static const struct stm32_hsem_mailbox_config stm32_hsem_mailbox_0_config = {
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.irq_config_func = stm32_hsem_mailbox_irq_config_func,
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.pclken = {
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.bus = DT_INST_CLOCKS_CELL(0, bus),
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.enr = DT_INST_CLOCKS_CELL(0, bits)
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},
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};
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/*
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* STM32 HSEM has its own LL_HSEM(low-level HSEM) API provided by the hal_stm32 module.
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* The ipm_stm32_hsem driver only picks up two semaphore IDs from stm32_hsem.h to simulate
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* a virtual mailbox device. So there will have only one instance.
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*/
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#define IPM_STM32_HSEM_INIT(inst) \
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BUILD_ASSERT((inst) == 0, \
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"multiple instances not supported"); \
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DEVICE_DT_INST_DEFINE(0, \
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&stm32_hsem_mailbox_init, \
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NULL, \
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&stm32_hsem_mailbox_0_data, \
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&stm32_hsem_mailbox_0_config, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
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&stm32_hsem_mailbox_ipm_dirver_api); \
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DT_INST_FOREACH_STATUS_OKAY(IPM_STM32_HSEM_INIT)
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