drivers/interrupt_controller: Add Intel VT-D interrupt remapping driver
Such interrupt remapping controller may be found along with Intel VT-D hardware. Its base-address is via ACPI, and it enables up to 64K interrupt indexes. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
e7be411d7b
commit
557b17076f
8 changed files with 427 additions and 0 deletions
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@ -18,3 +18,4 @@ zephyr_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_sources_ifdef(CONFIG_NPCX_MIWU intc_miwu.c)
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zephyr_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c)
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zephyr_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
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@ -64,4 +64,6 @@ source "drivers/interrupt_controller/Kconfig.gic"
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source "drivers/interrupt_controller/Kconfig.npcx"
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source "drivers/interrupt_controller/Kconfig.intel_vtd"
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endmenu
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25
drivers/interrupt_controller/Kconfig.intel_vtd
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25
drivers/interrupt_controller/Kconfig.intel_vtd
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@ -0,0 +1,25 @@
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# Intel VT-D interrupt remapping controller configuration
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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menuconfig INTEL_VTD_ICTL
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bool "Intel VT-D interrupt remapping controller"
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depends on ACPI && X86 && 64BIT
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select PCIE_MSI_MULTI_VECTOR
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help
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Such interrupt remapping hardware is provided through Intel VT-D
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technology. It's being used, currently, only for MSI/MSI-X
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multi-vector support. If you have such PCIe device requiring
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multi-vector support, you will need to enable this.
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if INTEL_VTD_ICTL
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config INTEL_VTD_ICTL_INIT_PRIORITY
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int "Initialization priority"
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default 0
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help
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This device should be initialized as soon as possible, before any
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other device that would require it for MSI/MSI-X multi-vector support.
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endif # INTEL_VTD_ICTL
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135
drivers/interrupt_controller/intc_intel_vtd.c
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135
drivers/interrupt_controller/intc_intel_vtd.c
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@ -0,0 +1,135 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_vt_d
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#include <errno.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <soc.h>
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#include <device.h>
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#include <init.h>
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#include <string.h>
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#include <zephyr.h>
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#include <arch/x86/intel_vtd.h>
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#include <drivers/interrupt_controller/intel_vtd.h>
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#include "intc_intel_vtd.h"
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static void vtd_write_reg64(const struct device *dev,
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uint16_t reg, uint64_t value)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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sys_write64(value, (base_address + reg));
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}
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static uint32_t vtd_read_reg(const struct device *dev, uint16_t reg)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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return sys_read32(base_address + reg);
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}
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static void vtd_send_cmd(const struct device *dev,
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uint16_t cmd_bit, uint16_t status_bit)
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{
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uintptr_t base_address = DEVICE_MMIO_GET(dev);
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sys_set_bit((base_address + VTD_GCMD_REG), cmd_bit);
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while (!sys_test_bit((base_address + VTD_GSTS_REG),
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status_bit)) {
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/* Do nothing */
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}
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}
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static int vtd_ictl_allocate_entries(const struct device *dev,
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uint8_t n_entries)
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{
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struct vtd_ictl_data *data = dev->data;
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int irte_idx_start;
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if ((data->irte_num_used + n_entries) > IRTE_NUM) {
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return -EBUSY;
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}
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irte_idx_start = data->irte_num_used;
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data->irte_num_used += n_entries;
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return irte_idx_start;
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}
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static uint32_t vtd_ictl_remap_msi(const struct device *dev,
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msi_vector_t *vector)
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{
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return VTD_MSI_MAP(vector->arch.irte);
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}
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static int vtd_ictl_remap(const struct device *dev,
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msi_vector_t *vector)
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{
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struct vtd_ictl_data *data = dev->data;
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uint8_t irte_idx = vector->arch.irte;
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memset(&data->irte[irte_idx], 0, sizeof(struct vtd_irte));
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data->irte[irte_idx].l.vector = vector->arch.vector;
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data->irte[irte_idx].l.dst_id = arch_curr_cpu()->id;
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data->irte[irte_idx].l.present = 1;
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return 0;
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}
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static int vtd_ictl_init(const struct device *dev)
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{
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struct vtd_ictl_data *data = dev->data;
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unsigned int key = irq_lock();
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uint64_t eime = 0;
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uint64_t irta;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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if (IS_ENABLED(CONFIG_X2APIC)) {
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eime = VTD_IRTA_EIME;
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}
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irta = VTD_IRTA_REG_GEN_CONTENT((uintptr_t)data->irte,
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IRTA_SIZE, eime);
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vtd_write_reg64(dev, VTD_IRTA_REG, irta);
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vtd_send_cmd(dev, VTD_GCMD_SIRTP, VTD_GSTS_SIRTPS);
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vtd_send_cmd(dev, VTD_GCMD_IRE, VTD_GSTS_IRES);
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printk("Intel VT-D up and running (status 0x%x)\n",
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vtd_read_reg(dev, VTD_GSTS_REG));
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irq_unlock(key);
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return 0;
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}
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static const struct vtd_driver_api vtd_api = {
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.allocate_entries = vtd_ictl_allocate_entries,
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.remap_msi = vtd_ictl_remap_msi,
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.remap = vtd_ictl_remap,
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};
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static struct vtd_ictl_data vtd_ictl_data_0;
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static const struct vtd_ictl_cfg vtd_ictl_cfg_0 = {
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(0)),
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};
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DEVICE_DEFINE(vtd_ictl, DT_INST_LABEL(0),
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vtd_ictl_init, device_pm_control_nop,
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&vtd_ictl_data_0, &vtd_ictl_cfg_0,
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PRE_KERNEL_1, CONFIG_INTEL_VTD_ICTL_INIT_PRIORITY, &vtd_api);
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58
drivers/interrupt_controller/intc_intel_vtd.h
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58
drivers/interrupt_controller/intc_intel_vtd.h
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@ -0,0 +1,58 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
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#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_
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#define VTD_INT_SHV BIT(3)
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#define VTD_INT_FORMAT BIT(4)
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/* We don't care about int_idx[15], since the size is fixed to 256,
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* it's always 0
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*/
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#define VTD_MSI_MAP(int_idx) \
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((0x0FEE << 20) | (int_idx << 5) | VTD_INT_SHV | VTD_INT_FORMAT)
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/* Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts */
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struct vtd_irte {
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struct {
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uint64_t present : 1;
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uint64_t fpd : 1;
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uint64_t dst_mode : 1;
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uint64_t redirection_hint : 1;
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uint64_t trigger_mode : 1;
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uint64_t delivery_mode : 3;
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uint64_t available : 4;
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uint64_t _reserved_0 : 3;
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uint64_t irte_mode : 1;
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uint64_t vector : 8;
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uint64_t _reserved_1 : 8;
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uint64_t dst_id : 32;
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} l;
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struct {
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uint64_t src_id : 16;
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uint64_t src_id_qualifier : 2;
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uint64_t src_validation_type : 2;
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uint64_t _reserved : 44;
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} h;
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} __packed;
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/* The table must be 4KB aligned, which is exactly 256 entries.
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* And since we allow only 256 entries as a maximum: let's align to it.
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*/
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#define IRTE_NUM 256
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#define IRTA_SIZE 7 /* size = 2^(X+1) where IRTA_SIZE is X 2^8 = 256 */
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struct vtd_ictl_data {
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struct vtd_irte irte[IRTE_NUM];
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int irte_num_used;
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};
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struct vtd_ictl_cfg {
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DEVICE_MMIO_ROM;
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};
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#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_INTEL_VTD_H_ */
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@ -32,6 +32,10 @@ extern "C" {
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struct x86_msi_vector {
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unsigned int irq;
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uint8_t vector;
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#ifdef CONFIG_INTEL_VTD_ICTL
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bool remap;
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uint8_t irte;
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#endif
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};
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typedef struct x86_msi_vector arch_msi_vector_t;
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122
include/arch/x86/intel_vtd.h
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122
include/arch/x86/intel_vtd.h
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@ -0,0 +1,122 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H
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#define ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H
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#ifndef _ASMLANGUAGE
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/*************\
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* Registers *
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\*************/
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#define VTD_VER_REG 0x000 /* Version */
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#define VTD_CAP_REG 0x008 /* Capability */
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#define VTD_ECAP_REG 0x010 /* Extended Capability */
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#define VTD_GCMD_REG 0x018 /* Global Command */
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#define VTD_GSTS_REG 0x01C /* Global Status */
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#define VTD_RTADDR_REG 0x020 /* Root Table Address */
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#define VTD_CCMD_REG 0x028 /* Context Command */
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#define VTD_FSTS_REG 0x034 /* Fault Status */
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#define VTD_FECTL_REG 0x038 /* Fault Event Control Register*/
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#define VTD_FEDATA_REG 0x03C /* Fault Event Data */
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#define VTD_FEADDR_REG 0x040 /* Fault Event Address */
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#define VTD_FEUADDR_REG 0x044 /* Fault Event Upper Address */
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#define VTD_AFLOG_REG 0x058 /* Advanced Fault Log */
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#define VTD_PMEN_REG 0x064 /* Protected Memory Enable */
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#define VTD_PLMBASE_REG 0x068 /* Protected Low Memory Base */
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#define VTD_PLMLIMIT_REG 0x06C /* Protected Low Memory Limit */
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#define VTD_PHMBASE_REG 0x070 /* Protected High Memory Base */
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#define VTD_PHMLIMIT_REG 0x078 /* Protected High Memory Limit */
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#define VTD_IQH_REG 0x080 /* Invalidation Queue Head */
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#define VTD_IQT_REG 0x088 /* Invalidation Queue Tail */
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#define VTD_IQA_REG 0x090 /* Invalidation Queue Address */
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#define VTD_ICS_REG 0x09C /* Invalidation Completion Status */
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#define VTD_IECTL_REG 0x0A0 /* Invalidation Completion Event Control */
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#define VTD_IEDATA_REG 0x0A4 /* Invalidation Completion Event Data */
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#define VTD_IEADDR_REG 0x0A8 /* Invalidation Completion Event Address */
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#define VTD_IEUADDR_REG 0x0AC /* Invalidation Completion Event Upper Address */
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#define VTD_IQERCD_REG 0x0B0 /* Invalidation Queue Error Record */
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#define VTD_IRTA_REG 0x0B8 /* Interrupt Remapping Table Address */
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#define VTD_PQH_REG 0x0C0 /* Page Request Queue Head */
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#define VTD_PQT_REG 0x0C8 /* Page Request Queue Tail */
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#define VTD_PQA_REG 0x0D0 /* Page Request Queue Address */
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#define VTD_PRS_REG 0x0DC /* Page Request Status */
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#define VTD_PECTL_REG 0x0E0 /* Page Request Event Control */
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#define VTD_PEDATA_REG 0x0E4 /* Page Request Event Data */
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#define VTD_PEADDR_REG 0x0E8 /* Page Request Event Address */
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#define VTD_PEUADDR_REG 0x0EC /* Page Request Event Upper Address */
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#define VTD_MTRRCAP_REG 0x100 /* MTRR Capability */
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#define VTD_MTRRDEF_REG 0x108 /* MTRR Default Type */
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#define VTD_MTRR_FIX64K_00000_REG 0x120 /* Fixed-range MTRR for 64K_00000 */
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#define VTD_MTRR_FIX16K_80000_REG 0x128 /* Fixed-range MTRR for 16K_80000 */
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#define VTD_MTRR_FIX16K_A0000_REG 0x130 /* Fixed-range MTRR for 16K_A0000 */
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#define VTD_MTRR_FIX4K_C0000_REG 0x138 /* Fixed-range MTRR for 4K_C0000 */
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#define VTD_MTRR_FIX4K_C8000_REG 0x140 /* Fixed-range MTRR for 4K_C8000 */
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#define VTD_MTRR_FIX4K_D0000_REG 0x148 /* Fixed-range MTRR for 4K_D0000 */
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#define VTD_MTRR_FIX4K_D8000_REG 0x150 /* Fixed-range MTRR for 4K_D8000 */
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#define VTD_MTRR_FIX4K_E0000_REG 0x158 /* Fixed-range MTRR for 4K_E0000 */
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#define VTD_MTRR_FIX4K_E8000_REG 0x160 /* Fixed-range MTRR for 4K_E8000 */
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#define VTD_MTRR_FIX4K_F0000_REG 0x168 /* Fixed-range MTRR for 4K_F0000 */
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#define VTD_MTRR_FIX4K_F8000_REG 0x170 /* Fixed-range MTRR for 4K_F8000 */
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#define VTD_MTRR_PHYSBASE0_REG 0x180 /* Variable-range MTRR Base0 */
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#define VTD_MTRR_PHYSMASK0_REG 0x188 /* Variable-range MTRR Mask0 */
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#define VTD_MTRR_PHYSBASE1_REG 0x190 /* Variable-range MTRR Base1 */
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#define VTD_MTRR_PHYSMASK1_REG 0x198 /* Variable-range MTRR Mask1 */
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#define VTD_MTRR_PHYSBASE2_REG 0x1A0 /* Variable-range MTRR Base2 */
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#define VTD_MTRR_PHYSMASK2_REG 0x1A8 /* Variable-range MTRR Mask2 */
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#define VTD_MTRR_PHYSBASE3_REG 0x1B0 /* Variable-range MTRR Base3 */
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#define VTD_MTRR_PHYSMASK3_REG 0x1B8 /* Variable-range MTRR Mask3 */
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#define VTD_MTRR_PHYSBASE4_REG 0x1C0 /* Variable-range MTRR Base4 */
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#define VTD_MTRR_PHYSMASK4_REG 0x1C8 /* Variable-range MTRR Mask4 */
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#define VTD_MTRR_PHYSBASE5_REG 0x1D0 /* Variable-range MTRR Base5 */
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#define VTD_MTRR_PHYSMASK5_REG 0x1D8 /* Variable-range MTRR Mask5 */
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#define VTD_MTRR_PHYSBASE6_REG 0x1E0 /* Variable-range MTRR Base6 */
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#define VTD_MTRR_PHYSMASK6_REG 0x1E8 /* Variable-range MTRR Mask6 */
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#define VTD_MTRR_PHYSBASE7_REG 0x1F0 /* Variable-range MTRR Base7 */
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#define VTD_MTRR_PHYSMASK7_REG 0x1F8 /* Variable-range MTRR Mask7 */
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#define VTD_MTRR_PHYSBASE8_REG 0x200 /* Variable-range MTRR Base8 */
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#define VTD_MTRR_PHYSMASK8_REG 0x208 /* Variable-range MTRR Mask8 */
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#define VTD_MTRR_PHYSBASE9_REG 0x210 /* Variable-range MTRR Base9 */
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#define VTD_MTRR_PHYSMASK9_REG 0x218 /* Variable-range MTRR Mask9 */
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#define VTD_VCCAP_REG 0xE00 /* Virtual Command Capability */
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#define VTD_VCMD 0xE10 /* Virtual Command */
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#define VTD_VCRSP 0xE20 /* Virtual Command Response */
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/* Global Command Register details */
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#define VTD_GCMD_CFI 23
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#define VTD_GCMD_SIRTP 24
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#define VTD_GCMD_IRE 25
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#define VTD_GCMD_QIE 26
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#define VTD_GCMD_WBF 27
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#define VTD_GCMD_EAFL 28
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#define VTD_GCMD_SFL 29
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#define VTD_GCMD_SRTP 30
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#define VTD_GCMD_TE 31
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/* Global Status Register details */
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#define VTD_GSTS_CFIS 23
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#define VTD_GSTS_SIRTPS 24
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#define VTD_GSTS_IRES 25
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#define VTD_GSTS_QIES 26
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#define VTD_GSTS_WBFS 27
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#define VTD_GSTS_EAFLS 28
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#define VTD_GSTS_SFLS 29
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#define VTD_GSTS_SRTPS 30
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#define VTD_GSTS_TES 31
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/* Interrupt Remapping Table Address Register details */
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#define VTD_IRTA_SIZE_MASK 0x00000000000000FF
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#define VTD_IRTA_EIME 11
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#define VTD_IRTA_ADDR_SHIFT 12
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#define VTD_IRTA_REG_GEN_CONTENT(addr, size, mode) \
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(0 | \
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(addr << VTD_IRTA_ADDR_SHIFT) | \
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(mode) | (size & VTD_IRTA_SIZE_MASK))
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL_VTD_H */
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80
include/drivers/interrupt_controller/intel_vtd.h
Normal file
80
include/drivers/interrupt_controller/intel_vtd.h
Normal file
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/*
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_INTEL_VTD_H_
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#define ZEPHYR_INCLUDE_DRIVERS_INTEL_VTD_H_
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|
||||
#include <drivers/pcie/msi.h>
|
||||
|
||||
typedef int (*vtd_alloc_entries_f)(const struct device *dev,
|
||||
uint8_t n_entries);
|
||||
|
||||
typedef uint32_t (*vtd_remap_msi_f)(const struct device *dev,
|
||||
msi_vector_t *vector);
|
||||
|
||||
typedef int (*vtd_remap_f)(const struct device *dev,
|
||||
msi_vector_t *vector);
|
||||
|
||||
struct vtd_driver_api {
|
||||
vtd_alloc_entries_f allocate_entries;
|
||||
vtd_remap_msi_f remap_msi;
|
||||
vtd_remap_f remap;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Allocate contiguous IRTEs
|
||||
*
|
||||
* @param dev Pointer to the device structure for the driver instance
|
||||
* @param n_entries How many IRTE to allocate
|
||||
*
|
||||
* Note: It will try to allocate all, or it will fail.
|
||||
*
|
||||
* @return The first allocated IRTE index, or -EBUSY on failure
|
||||
*/
|
||||
static inline int vtd_allocate_entries(const struct device *dev,
|
||||
uint8_t n_entries)
|
||||
{
|
||||
const struct vtd_driver_api *api =
|
||||
(const struct vtd_driver_api *)dev->api;
|
||||
|
||||
return api->allocate_entries(dev, n_entries);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate the MSI Message Address data for the given vector
|
||||
*
|
||||
* @param dev Pointer to the device structure for the driver instance
|
||||
* @param vector A valid allocated MSI vector
|
||||
*
|
||||
* @return The MSI Message Address value
|
||||
*/
|
||||
static inline uint32_t vtd_remap_msi(const struct device *dev,
|
||||
msi_vector_t *vector)
|
||||
{
|
||||
const struct vtd_driver_api *api =
|
||||
(const struct vtd_driver_api *)dev->api;
|
||||
|
||||
return api->remap_msi(dev, vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Remap the given vector
|
||||
*
|
||||
* @param dev Pointer to the device structure for the driver instance
|
||||
* @param vector A valid allocated MSI vector
|
||||
*
|
||||
* @return 0 on success, a negative errno otherwise
|
||||
*/
|
||||
static inline int vtd_remap(const struct device *dev,
|
||||
msi_vector_t *vector)
|
||||
{
|
||||
const struct vtd_driver_api *api =
|
||||
(const struct vtd_driver_api *)dev->api;
|
||||
|
||||
return api->remap(dev, vector);
|
||||
}
|
||||
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DRIVERS_INTEL_VTD_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue