From 55769dc5014bad2e99e5aa993769e25c15b725b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Mon, 9 Jun 2025 22:57:10 +0200 Subject: [PATCH] drivers: mdio: fix typo in macro name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit s/SOC_SERIES_STM32F1X/CONFIG_SOC_SERIES_STM32F1X/ Signed-off-by: Benjamin Cabé --- drivers/mdio/mdio_stm32_hal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mdio/mdio_stm32_hal.c b/drivers/mdio/mdio_stm32_hal.c index de9672fda94..4a46596e404 100644 --- a/drivers/mdio/mdio_stm32_hal.c +++ b/drivers/mdio/mdio_stm32_hal.c @@ -99,7 +99,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth) tmpreg1 &= ETH_MACMIIAR_CR_MASK; /* Set CR bits depending on CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC value */ -#ifdef SOC_SERIES_STM32F1X +#ifdef CONFIG_SOC_SERIES_STM32F1X if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) && (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) { /* CSR Clock Range between 20-35 MHz */ @@ -112,7 +112,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth) /* CSR Clock Range between 60-72 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42; } -#else /* SOC_SERIES_STM32F2X */ +#else /* CONFIG_SOC_SERIES_STM32F2X */ if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) && (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) { /* CSR Clock Range between 20-35 MHz */ @@ -129,7 +129,7 @@ static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth) /* CSR Clock Range between 100-120 MHz */ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; } -#endif /* SOC_SERIES_STM32F2X */ +#endif /* CONFIG_SOC_SERIES_STM32F1X */ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;