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boards: mimxrt1024_evk: enable mcux ethernet driver and pins

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Enables the mcux ethernet driver and pin muxes on the
mimxrt1024_evk board in the same way as is done on the
mimxrt1020_evk and mimxrt1050_evk.

Documentation updated accordingly.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
This commit is contained in:
Mikkel Jakobsen 2021-08-23 09:33:00 +02:00 • committed by Christopher Friedt
commit 5524edb935
4 changed files with 99 additions and 0 deletions
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7
boards/arm/mimxrt1024_evk/Kconfig.defconfig
View file

@ -18,4 +18,11 @@ config FLASH_MCUX_FLEXSPI_NOR
config FLASH_MCUX_FLEXSPI_XIP
default y if FLASH
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_MIMXRT1024_EVK

26
boards/arm/mimxrt1024_evk/doc/index.rst
View file

@ -79,6 +79,8 @@ features:
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
@ -101,6 +103,30 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW4 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_04 | ENET_RST | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_08 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | ENET_RX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | ENET_RX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | ENET_RX_ER | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | ENET_TX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_15 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | ENET_INT | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_41 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
System Clock
============

7
boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts
View file

@ -80,6 +80,13 @@
};
};
&enet {
status = "okay";
ptp {
status = "okay";
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;

59
boards/arm/mimxrt1024_evk/pinmux.c
View file

@ -8,6 +8,13 @@
#include <fsl_iomuxc.h>
#include <fsl_gpio.h>
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
static gpio_pin_config_t enet_gpio_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0,
.interruptMode = kGPIO_NoIntmode
};
#endif
static int mimxrt1024_evk_init(const struct device *dev)
{
@ -43,7 +50,59 @@ static int mimxrt1024_evk_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0x31);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB829);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
/* Initialize ENET_INT GPIO */
GPIO_PinInit(GPIO1, 4, &enet_gpio_config);
GPIO_PinInit(GPIO1, 22, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 22, 1);
GPIO_WritePinOutput(GPIO1, 4, 0);
#endif
return 0;
}
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
static int mimxrt1024_evk_phy_reset(const struct device *dev)
{
/* RESET PHY chip. */
k_busy_wait(USEC_PER_MSEC * 10U);
GPIO_WritePinOutput(GPIO1, 4, 1);
return 0;
}
#endif
SYS_INIT(mimxrt1024_evk_init, PRE_KERNEL_1, 0);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
SYS_INIT(mimxrt1024_evk_phy_reset, PRE_KERNEL_2, 1);
#endif