soc: stm32: Add support for stm32h745xx SoC

add stm32h745xx SoC and corresponding device tree

Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>

dts/arm/st/h7/stm32h745.dtsi

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov
+ * AlexanderKozhinov@yandex.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/h7/stm32h7_dualcore.dtsi>
+
+/ {
+	/*
+	* The RAM memories placed here can be used by both cores M4/M7
+	* For more information see reference manual and datasheet to STM32H745
+	*/
+
+	/* system data RAM accessible over over AXI bus */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(512)>;
+		compatible = "mmio-sram";
+	};
+
+	/* system data RAM accessible over over AHB bus */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(288)>;
+		compatible = "mmio-sram";
+	};
+
+	/* system data RAM accessible over over AHB bus */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(64)>;
+		compatible = "mmio-sram";
+	};
+};

dts/arm/st/h7/stm32h745Xi_m4.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov
+ * AlexanderKozhinov@yandex.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h745.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash1: flash@8100000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08100000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};

dts/arm/st/h7/stm32h745Xi_m7.dtsi

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Alexander Kozhinov
+ * AlexanderKozhinov@yandex.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/h7/stm32h745.dtsi>
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+	};
+
+	soc {
+		flash-controller@52002000 {
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+	};
+};

soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series

@@ -12,4 +12,8 @@ source "soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*"
 config SOC_SERIES
 	default "stm32h7"
 
+config DMA_STM32_V1
+	default y
+	depends on DMA_STM32
+
 endif # SOC_SERIES_STM32H7X

soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx

@@ -0,0 +1,15 @@
+# ST STM32H745X MCU configuration options
+
+# Copyright (c) 2020 Alexander Kozhinov
+# AlexanderKozhinov@yandex.com
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32H745XX
+
+config SOC
+	default "stm32h745xx"
+
+config NUM_IRQS
+	default 150
+
+endif # SOC_STM32H745XX

soc/arm/st_stm32/stm32h7/Kconfig.series

@@ -11,8 +11,10 @@ config SOC_SERIES_STM32H7X
 	select SOC_FAMILY_STM32
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
+	select HAS_SWO
 	select REQUIRES_FULL_LIBC
 	select USE_STM32_HAL_RCC_EX if CPU_CORTEX_M4
+	select USE_STM32_HAL_CORTEX
 	help
 	  Enable support for STM32H7 MCU series
 

soc/arm/st_stm32/stm32h7/Kconfig.soc

@@ -13,6 +13,10 @@ config SOC_STM32H743XX
 	select CPU_CORTEX_M7
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 
+config SOC_STM32H745XX
+	bool "STM32H745XX"
+	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
+
 config SOC_STM32H747XX
 	bool "STM32H747XX"
 	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7