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soc: esp32: Fix linker scripts

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Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2023-05-29 19:29:47 +02:00 • committed by Carles Cufí
commit 548e8b717d
2 changed files with 7 additions and 11 deletions
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10
soc/xtensa/esp32/default.ld
View file

@ -30,19 +30,19 @@
#define ROMABLE_REGION ROM
#ifdef CONFIG_FLASH_SIZE
#define ROM_SIZE CONFIG_FLASH_SIZE
#define FLASH_SIZE CONFIG_FLASH_SIZE
#else
#define ROM_SIZE 0x400000
#define FLASH_SIZE 0x400000
#endif
#ifdef CONFIG_BOOTLOADER_ESP_IDF
#define IROM_SEG_ORG 0x400D0020
#define IROM_SEG_LEN 0x330000-0x20
#define IROM_SEG_LEN FLASH_SIZE-0x20
#define IROM_SEG_ALIGN 0x4
#define IRAM_SEG_LEN 0x20000
#else
#define IROM_SEG_ORG 0x400D0000
#define IROM_SEG_LEN 0x330000
#define IROM_SEG_LEN FLASH_SIZE
#define IROM_SEG_ALIGN 0x10000
#define IRAM_SEG_LEN 0x13000
#endif
@ -51,7 +51,7 @@ MEMORY
{
mcuboot_hdr (RX): org = 0x0, len = 0x20
metadata (RX): org = 0x20, len = 0x20
ROM (RX): org = 0x40, len = ROM_SIZE - 0x40
ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40
#ifdef CONFIG_ESP32_NETWORK_CORE
iram0_0_seg(RX): org = 0x40080000, len = 0x08000

8
soc/xtensa/esp32s3/default.ld
View file

@ -46,19 +46,15 @@
#endif
#ifdef CONFIG_BOOTLOADER_ESP_IDF
#define IROM_SEG_ORG 0x42000020
#define IROM_SEG_LEN FLASH_SIZE-0x20
#define IROM_SEG_ALIGN 0x4
#else
#define IROM_SEG_ORG 0x42000000
#define IROM_SEG_LEN FLASH_SIZE
#define IROM_SEG_ALIGN 0x10000
#endif
#define IROM_SEG_ALIGN 0x10000
MEMORY
{
mcuboot_hdr (RX): org = 0x0, len = 0x20