soc/xtensa/intel_adsp: Upstream updates
Significant rework of the Intel Audio DSP SoC/board layers. Includes
code from the following upstream commits:
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 25 16:34:36 2020 +0100
xtesna: adsp: use 50k ticks per sec for audio
Audio needs high resolution scheduling so schedule to nearest 20uS.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 24 13:59:01 2020 -0700
soc/xtensa/intel_adsp: Remove sof-config.h includes
This header isn't used any more, and in any case shouldn't be included
by SoC-layer Zephyr headers that need to be able to build without SOF.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat Jun 20 15:42:58 2020 -0700
soc/intel_adsp: Leave interrupts disabled at MP startup
This had some code that was pasted in from esp32 that was inexplicably
enabling interrupts when starting an auxiliary CPU. The original
intent was that the resulting key would be passed down to the OS, but
that's a legacy SMP mechanism and unused. What it actually did was
SET the resulting value in PS.INTLEVEL, enabling interrupts globally
before the CPU is ready to handle them.
Just remove. The system doesn't need to enable interrupts until the
entrance to the first user thread on this CPU, which will do it
automatically as part of the context switch.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 13:57:54 2020 +0300
dts: intel_cavs: Add required label
Add required label fixing build for CAVS15, 20, 25.
Fixes following errors:
...
devicetree error: 'label' is marked as required in 'properties:' in
bindings/interrupt-controller/intel,cavs-intc.yaml,
but does not appear in
...
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:19:56 2020 +0300
soc: cavs_v18: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 15:12:25 2020 +0300
soc: cavs_v20: Remove dts_fixup and fix build
Remove unused now dts_fixup.h and fix build with the recent code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 23 14:59:23 2020 +0300
soc: cavs_v25: Remove dts_fixup fix build
Remove unused now dts_fixup and fix build with the latest code base.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:29:06 2020 +0300
soc: intel_adsp: Remove unused functions
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:53:58 2020 +0300
soc: intel_adsp: Clean up soc.h
Remove unused or duplicated definitions.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 17:02:23 2020 +0300
soc: intel_adsp: De-duplicate soc.h
Move soc.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:54:19 2020 +0300
soc: intel_adsp: Remove duplicated io.h
Move duplicated io.h to common SOC area.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:46 2020 +0300
cmake: Correct SOC_SERIES name for byt and bdw
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 12 12:39:02 2020 +0300
soc: intel_adsp: Build bootloader only for specific SOCs
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Thu Jun 11 13:46:25 2020 +0100
boards: xtensa: adsp: add byt and bdw boards WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 10 10:01:29 2020 -0700
soc/intel_adsp: Make the HDA timer the default always
The CAVS_TIMER was originally written because the CCOUNT values are
skewed between SMP CPUs, so it's the default when SMP=y. But really
it should be the default always, the 19.2 MHz timer is plenty fast
enough to be the Zephyr cycle timer, and it's rate is synchronized
across the whole system (including the host CPU), making it a better
choice for timing-sensitive applications.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:21:43 2020 +0300
soc: cavs_v25: Enable general samples build
Enables general samples build for SOC cavs_v25.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 15:13:53 2020 +0300
soc: cavs_v20: Enable general samples build
Enable general sample build.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:35:13 2020 +0300
soc: cavs_v18: Fix build general samples
Fix building general samples for CAVS18.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 14:22:40 2020 +0300
soc: intel_adsp: Add support for other SOCs
Support other SOCs in the "ready" message to the Host.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 10 13:25:39 2020 +0300
soc: intel_adsp: Move adsp.c to common SOC area
Move adsp.c to common and clean makefiles.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 17:18:18 2020 +0300
boards: intel_adsp: Remove dependency on SOF
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 14:29:44 2020 +0100
soc: xtensa: cavs: build now good for cavs20 + 25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 15:57:01 2020 +0300
soc: cavs_v15: Fix build for hello_world
Fix build for other then audio/sof targets.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:50:12 2020 +0300
sample: audio/sof: Remove old overlays
Removing old overlays used to switch logging backend.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 15:02:01 2020 +0300
soc: intel_adsp: Correct TEXT area
Correct HEADER_SPACE and put TEXT to:
(HP_SRAM_WIN0_BASE + HP_SRAM_WIN0_SIZE + VECTOR_TBL_SIZE)
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:44:47 2020 +0300
soc: intel_adsp: Trivial syntax cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 14:41:07 2020 +0300
soc: intel_adsp: Fix bootloader script path
Make it possible to find linker script if build is done not inside
ZEPHYR_BASE.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 12:10:17 2020 +0100
soc: xtensa: cavs20/25: fix build with new headers - WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 9 13:35:38 2020 +0300
soc: intel_adsp: Fix include headers
Fixes include headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 9 10:38:50 2020 +0100
soc: xtensa: cav18: updated headers- WIP
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Fri May 1 15:29:26 2020 -0700
soc/xtensa/intel_adsp: Clean up MP config logic
CONFIG_MP_NUM_CPUS is a platform value, indicating the number of CPUs
for which the Zephyr image is built. This is the value kernel and
device code should use to predicate questions like "is there more than
one CPU?"
CONFIG_SMP is an application tunable, controlling whether or not the
kernel schedules threads on CPUs other than the first one. This is
orthogonal to MP_NUM_CPUS: it's possible to build a "SMP" kernel on a
uniprocessor system or have a UP kernel on a MP system if the other
cores are used for non-thread application code.
CONFIG_SCHED_IPI_SUPPORTED is a platform flag telling an SMP kernel
whether or not it can synchronously signal other CPUs of scheduler
state changes. It should be inspected only inside the scheduler (or
other code that uses the API). This should be selected in kconfig by
soc layer code, or by a driver that implements the feature.
CONFIG_IPM_CAVS_IDC is a driver required to implement IPI on this
platform. This is what we should use as a predicate if we have
dependence on the IPM driver for a platform feature.
These were all being sort of borged together in code. Split them up
correctly, allowing the platform MP layer to be unit tested in the
absence of SMP (c.f. tests/kernel/mp), and SMP kernels with only one
CPU (which is pathlogical in practice, but also a very good unit test)
to be built.
Also removes some dead linker code for SMP-related sections that don't
exist in Zephyr.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:41:55 2020 +0100
soc: xtensa: bootloader - use linker script
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Jun 8 16:26:18 2020 +0100
soc: xtensa: further fix headers - WIP
Simplify the directory structure, WIP for cavs20 and cavs25
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Jun 8 12:59:30 2020 +0300
soc: cavs_v15: Remove unneeded include
Remove include fixing build.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Jun 7 12:37:35 2020 +0100
soc:xtensa: adsp: remove sof specific code from soc headers
TODO: v1.8+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 23:19:37 2020 -0700
intel_adsp_*/doc: fix duplicate .rst labels
Quick fix purely to make the build green again.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Thu Jun 4 22:34:40 2020 -0700
samples/audio/sof: use OVERLAY_CONFIG to import apollolake_defconfig
This reverts commit 21f16b5b1d29fca83d1b62b1b75683b5a1bc2935 that
copied it here instead.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri Jun 5 12:34:48 2020 +0300
soc: intel_adsp: Move soc_mp to common
Moving soc_mp to common SOC area, it still needs fixes for taking
number of cores from Zephyr Kconfig, etc.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 16:05:06 2020 +0300
soc: intel_adsp: Move memory.h from lib/
For those files from SOF referencing platform/lib/memory.h we have
include.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 15:20:09 2020 +0300
soc: intel_adsp: Rename platform.h to soc.h
Rename to prevent including it from SOF.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:47:55 2020 +0300
soc: intel_adsp: Move headers
Move headers to more convenient place
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Jun 4 11:21:51 2020 +0300
soc: intel_adsp: More SOC cleaning
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Marc Herbert <marc.herbert@intel.com>
Date: Mon Jun 1 15:31:34 2020 -0700
samples/audio/sof: import sof/src/arch/xtensa/ apollolake_defconfig
Import modules/audio/sof/src/arch/xtensa/configs/apollolake_defconfig
into prj.conf and new boards/up_squared_adsp.conf
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:07:40 2020 +0100
soc:xtensa: adsp: let SOF configure the DSP for audio
Let SOF do this for the moment.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 15:06:20 2020 +0100
soc: xtensa: cavs: remove headers similar to cavs15
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 15:58:38 2020 +0300
soc: intel_adsp: Move ipc header to common
Remove duplicated headers from CAVS to common SOC part
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Jun 3 13:02:09 2020 +0300
soc: cavs_v15: Remove unneeded headers
Remove also from CAVS15.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 18:34:11 2020 +0300
Remove more headers
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:12:09 2020 +0100
soc: xtensa: remove cavs sod headers for drivers and trace.
Duplicate cavs15 headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Jun 3 14:05:12 2020 +0100
samples: move sof dai, dma and clk configs to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 17:38:45 2020 +0300
soc: intel_adsp: Remove more duplicated headers
Remove more headers
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue Jun 2 15:50:03 2020 +0100
samples: sof: remove pm realted files.
Use the SOF versions.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 16:55:40 2020 +0300
WIP: Strip lib from include path
WIP, pushed for sync
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:44:33 2020 +0300
soc: intel_adsp: Remove more headers
Remove even more common headers
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Jun 2 14:00:47 2020 +0300
soc: intel_adsp: Remove SOF headers
The headers would be used by audio/sof app directly from SOF module.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Sat May 30 11:01:26 2020 -0700
soc/intel_adsp: Alternative log reading script
This script speaks the same protocol and works with the same firmware,
but:
* Is a single file with no dependencies outside the python3 standard
library and can be run out-of-tree (i.e. with setups where the
firmware is not built on the device under test)
* Operates in "tail" mode, where it will continue polling for more
output, making it easier to watch a running process and acting more
like a conventional console device.
* Has no dependence on the diag_driver kernel module (it reads the DSP
SRAM memory directly from the BAR mapping in the PCI device)
* Is MUCH smaller than the existing tool.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 28 16:17:51 2020 +0300
Decrease HEP pool size to 192000
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:27:00 2020 +0100
soc: xtensa: cavs25: complete support for cavs25
Builds, not tested on qmeu due to missing SOF ROM (TODO)
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:24:26 2020 +0100
soc: xtensa: cavs20: complete cavs20 support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:22:13 2020 +0100
soc: xtensa: cavs18: complete boot support
Now boots on qemu.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:19:23 2020 +0100
soc: xtensa: cavs15: use cavs15 instead of apl as linker soc name
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 29 10:16:06 2020 +0100
TODO: samples: sof: work around missing trace symbols.
Disable local trace.
Needs trace updates finished before this can be removed.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:57:19 2020 +0100
dts: xtensa: rename apl to cavs15 DTS
This DTS is used by more than APL SOC. i.e. all CAVS15 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:52:20 2020 +0100
west: commands: sign: Add signing support for other CAVS targets
Sign for CAVS15, CAVS18, CAVS20 and CAVS25 SOCs
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:50:07 2020 +0100
boards: xtensa: cavs: used Zephyr mask macro
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed May 27 15:49:46 2020 +0100
soc: xtensa: move code to SOF
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 26 11:40:36 2020 +0100
soc: xtensa: use SOF versions of clk
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:38:45 2020 +0300
soc: intel_adsp: Send FW ready for non SOF configuration
Configure windows and send FW ready when used without SOF, should be
loaded with fw_loader script.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 18:02:22 2020 +0300
soc: intel_adsp: Use SOF version of the file
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:47:27 2020 +0300
soc: intel_adsp: Clean up include headers
Remove SOF mentions from the SOC headers.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:43:05 2020 +0300
soc: intel_adsp: Move SOF specific code to samples/audio/sof
Move SOF specific code to the SOF sample.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:39:42 2020 +0300
soc: intel_adsp: Use SOF module's version of mem_window.c
Use exact copy from SOF module.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 17:36:41 2020 +0300
soc: intel_adsp: Use exact copy from SOF module
Use SOF module verion of the clk.c
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 25 14:03:35 2020 +0300
soc: xtensa: Add {SOC_FAMILY}/common/include path
Add ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include path if exist.
Fixes issues for xtensa SOCs.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:18:50 2020 +0100
soc: xtensa: cavs common: fix headers for build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:10:57 2020 +0100
soc: xtensa: adsp: add so_inthandlers.h for Intel platforms
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 25 16:08:26 2020 +0100
cmake: xtensa: select correct compiler per CAVS target.
TODO: what about XCC ?
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue May 19 14:59:26 2020 +0300
boards: up_squared_adsp: Move SOF configuration to samples
Move SOF-specific configuration to samples/audio/sof prj.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 15 15:29:50 2020 +0300
soc: intel_adsp: Move SOF code to modules/audio/sof
Move SOF dependent code out of SOC area.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 14 17:30:38 2020 +0300
Move task_main_start() to audio/sof sample
Start task_main_start() from main of audio/sof sample.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed May 13 15:37:20 2020 +0300
Rename up_xtreme_adsp to intel_adsp_cavs18
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon Apr 27 14:12:59 2020 +0300
Add sample audio/sof for SOF initialization
Add dedicated sample where we put SOF specific initialization.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 18:49:36 2020 +0300
WIP: soc: cavs_v18: Cleanup
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:44:06 2020 +0300
soc: cavs_v15: Move soc init to common part
Moving SOC init to the right place.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Mon May 11 15:02:28 2020 +0300
soc: intel_adsp: Move common part to special dir
Moving common part to common/adsp.c
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Fri May 8 14:37:50 2020 +0300
boards: up_xtreme_adsp: Add initial up_xtreme_adsp board
Add initial board copying existing up_squared_adsp board and using
CAVS1.8 SOC family.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu May 7 15:30:51 2020 +0300
soc: intel_adsp: Generalize bootloader
Move bootloader to soc/xtensa/intel_adsp making it available for other
boards.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:31:00 2020 +0100
boards: xtensa: up_squared: Add support for all CAVS
Add boot support for all CAVS versions. TODO: needs to be made common
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Tue May 5 21:25:34 2020 +0100
soc: xtensa: intel_adsp: Manage cache for DMA descriptors
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 21:10:50 2020 +0100
soc: xtensa: adsp: use 24M567 clock
Use audio clock
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon May 4 10:04:01 2020 +0100
xtensa: soc: adsp: enable system agent
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:03:07 2020 +0100
soc: xtensa: intel_adsp: increase mem pool to 192k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 15:02:31 2020 +0100
soc: xtensa: intel_adsp: re-enable DMA trace
Buffer will be empty (as trace items sent to Zephyr LOG) but
logic is running.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 11:18:55 2020 +0100
soc: xtensa: intel: dont use uncache region yet.
Some code was still using this region. Use later.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun May 3 10:07:28 2020 +0100
soc: xtensa: intel_adsp: fix notifier init
Topology now loads.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:18:38 2020 +0100
boards: up2: Need to use sof config for bootloader
This will need uncoupled at some point. For testing today.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 21:16:38 2020 +0100
boards: up2: increase heap to 128k
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:35:19 2020 +0300
boards: up_squared_adsp: Use bigger HEAP
Use HEAP from old demo.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri May 1 16:06:32 2020 +0100
soc: xtensa: intel_adsp: Fix config.h naming collisions
Rename sof version to sof-config.h
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Thu Apr 30 11:22:42 2020 +0300
Small cleanups
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 22:00:44 2020 +0300
tests: sof/audio: Test ll scheduler
Add more tests for scheduler.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 29 18:38:35 2020 +0300
tests: Add first schedule test
Add initial test for testing scheduling.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 29 13:36:23 2020 +0100
soc: xtensa: rmeove build warnings
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 18:04:33 2020 +0300
soc/intel_adsp: Register sof logging
Register sof logging for tracing
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 14:16:55 2020 +0300
boards: up_squared_adsp: Define HEAP_MEM_POOL_SIZE
Define HEAP_MEM_POOL_SIZE when SOF enabled.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 28 10:09:20 2020 +0300
tests: audio/sof: Add interrupt API for testing
Add initial interrupt API for testing.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 15:54:28 2020 +0100
soc: xtensa: adsp: Update linker script for SOF sections.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 27 11:20:01 2020 +0100
soc: xtensa: adsp: send SOF FW metadata as boot message
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 26 21:47:20 2020 +0100
soc: xtensa: adsp: re-enable all SOF IP init.
Do all SOF IP init.
TODO: ATOMCTL, WFI on LX6
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sat Apr 25 15:30:40 2020 +0100
soc: xtensa: irq: Make sure IPC IRQ is registered.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 20:56:09 2020 +0300
tests: sof: Enable console
Enable console for the test.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 17:57:22 2020 +0300
soc: cavs_v15: Fix XTENSA_KERNEL_CPU_PTR_SR
Use correct value for XTENSA_KERNEL_CPU_PTR_SR.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Wed Apr 22 14:48:31 2020 +0300
tests: audio/sof: Add tests for alloc API testing
Add initial tests for allocation API testing. Can be extended for
other later.
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 17:49:32 2020 +0300
logging: Enable xtensa simulator backend for ADSP
Enable xtensa simulator backend for SOC_FAMILY_INTEL_ADSP.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 20:58:30 2020 +0100
soc: xtensa: add common cpu logic
Support for additional cores.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Date: Tue Apr 21 10:11:07 2020 +0300
Update west.yaml to point to the latest repo
Update west.yaml
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:17:01 2020 +0100
soc: xtensa: cavs: Fix build for clk.c on cavs18+
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:31 2020 +0100
soc: xtensa: cavs15: removed unused headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:05:09 2020 +0100
soc: xtensa: cavs25: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:52 2020 +0100
soc: xtensa: cavs20: align with SOF headers
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 16:03:09 2020 +0100
soc: xtensa: cavs18: Align with SOF headers.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Apr 20 11:42:39 2020 +0100
west: sof: Updated to latest version.
Now builds, links and runs SOF code (but not to FW ready).
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Sun Apr 19 13:28:53 2020 +0100
xtensa: intel adsp: build in SOF symbols if CONFIG_SOF
Code now fully links against SOF. Needs to be run tested.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:19:28 2020 -0700
DO NOT MERGE: temporarily add thesoftproject as remote for sof module
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Wed Apr 15 10:33:40 2020 -0700
ipm: cavs_idc: use the IPC/IDC definitions in SoC
The SoC definitions have the necessary IPC/IDC bits so there is
no need to define them separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 14:30:20 2020 +0100
TODO: config: Use static config for SOF module.
TODO: needs to be generated as part of SOF kconfig
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Fri Apr 10 21:56:07 2020 +0100
HACK: Add SOF into build
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:55:15 2020 +0100
west: modules: Add SOF audio module.
Add support for building SOF as a Zephyr module. This is the starting
point for add SOF audio into Zephyr. Currently builds but does not use
any symbols yet.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:48:48 2020 +0100
WIP soc: adsp-cavs15: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Apr 15 13:43:44 2020 +0100
WIP soc: adsp-common: Use same include directory structure as SOF
Use the same directory structure as SOF to simplify porting and allow
SOF to build without Zephyr until porting work is complete.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:36:32 2020 +0000
WIP: soc: adsp-common: cache is common across all Intel ADSP platforms
De-duplicate soc.h cache definitions.
TODO: this needs done for other common functions.
TODO: need to fix include path
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:43 2020 -0700
WIP: soc: cavs25: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:07:12 2020 -0700
WIP: soc: cavs20: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 30 11:06:40 2020 -0700
WIP: soc: cavs18: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 12:37:17 2020 -0700
soc: intel_adsp: use main_entry.S in common for cavs_v15
The files are identical anyway.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:38:14 2020 -0700
soc: intel_adsp/cavs_v15: link common code
Let cavs_v15 link against the code compiled under common/.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 13:08:28 2020 +0000
WIP: soc: common: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:37:32 2020 +0000
WIP soc: adsp-cavs15: build power down support
Build the power down support for CAVS1.5
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 12:40:17 2020 +0000
WIP: soc: cavs15: Import SOF SoC support
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 16 14:30:08 2020 +0000
soc: cavs15: Add missing SHIM registers.
SOF commit 2746df76b98f21d3e0b2c5cd4fe405c9a42014a4
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Mon Mar 9 15:43:01 2020 +0000
xtensa: intel_adsp/cavs_v15: fix usage of LP SRAM power gating
Remove LSPGCTL as it can cause confusion, use SHIM_LSPGCTL instead.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Date: Wed Feb 26 15:28:48 2020 +0000
boards: up_squared_adsp: Use local xtensa HAL instead of SDK HAL
SDK HAL is deprecated for Intel ADSP SoCs so fix and use local HAL
module.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 10:45:15 2020 -0700
soc: add Intel Audio DSP SoC family
This creates a SoC family for the audio DSPs on various
Intel CPUs. The intel_apl_adsp is being moved into
this family as well, since it is part of the CAVS v1.5
series of DSPs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Date: Mon Mar 30 11:29:02 2020 -0700
soc: xtensa: add CMakeLists.txt
Add CMakeLists.txt under soc/xtensa so that CMakeLists.txt
inside each SoC directory will be included, similar to
what ARM and RISCV have.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:43 2020 -0700
Revert "boards: up_squared_adsp: Add flasher script"
This reverts commit 80f295a9dd.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:32 2020 -0700
Revert "boards: up_squared_adsp: Update logtool tool"
This reverts commit 7770d182c1.
Author: Andy Ross <andrew.j.ross@intel.com>
Date: Wed Jun 17 12:30:23 2020 -0700
Revert "soc: intel_adsp: Generalize bootloader"
This reverts commit d6a33ef467.
Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
soc: xtensa; intel: remove sof-config.h - SQUASH
No longer used.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Andy Ross
Anas Nashif
parent
ec6a98e5e1
commit
544a38ee62
102 changed files with 6673 additions and 859 deletions
33
soc/xtensa/intel_adsp/common/CMakeLists.txt
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33
soc/xtensa/intel_adsp/common/CMakeLists.txt
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@ -0,0 +1,33 @@
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# Intel CAVS SoC family CMake file
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#
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_interface_library_named(INTEL_ADSP_COMMON)
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zephyr_library_named(intel_adsp_common)
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zephyr_library_include_directories(include)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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set_source_files_properties(adsp.c PROPERTIES COMPILE_FLAGS -std=gnu99)
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zephyr_library_sources(adsp.c)
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zephyr_library_sources(main_entry.S)
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zephyr_library_sources(soc.c)
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zephyr_library_sources(soc_mp.c)
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zephyr_library_sources(printk_out.c)
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zephyr_library_link_libraries(INTEL_ADSP_COMMON)
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target_include_directories(INTEL_ADSP_COMMON INTERFACE include)
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target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common)
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# Common CAVS code
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if(CONFIG_SOC_SERIES_INTEL_CAVS_V15 OR
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CONFIG_SOC_SERIES_INTEL_CAVS_V18 OR
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CONFIG_SOC_SERIES_INTEL_CAVS_V20 OR
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CONFIG_SOC_SERIES_INTEL_CAVS_V25)
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zephyr_library_sources(soc.c)
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zephyr_library_sources(soc_mp.c)
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include(bootloader.cmake)
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endif()
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136
soc/xtensa/intel_adsp/common/adsp.c
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136
soc/xtensa/intel_adsp/common/adsp.c
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@ -0,0 +1,136 @@
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/* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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* Keyon Jie <yang.jie@linux.intel.com>
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* Rander Wang <rander.wang@intel.com>
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* Janusz Jankowski <janusz.jankowski@linux.intel.com>
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*/
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#include <device.h>
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#include <init.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(sof);
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#include <ipc.h>
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#include <soc/shim.h>
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#include <adsp/io.h>
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#include <cavs/mailbox.h>
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#define SRAM_WINDOW_HOST_OFFSET(x) (0x80000 + x * 0x20000)
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static const struct adsp_ipc_fw_ready fw_ready_apl
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__attribute__((section(".fw_ready"))) __attribute__((used)) = {
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.hdr = {
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.cmd = ADSP_IPC_FW_READY,
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.size = sizeof(struct adsp_ipc_fw_ready),
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},
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.version = {
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.hdr.size = sizeof(struct adsp_ipc_fw_version),
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.micro = 0,
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.minor = 1,
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.major = 0,
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.build = 0,
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.date = __DATE__,
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.time = __TIME__,
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.tag = "zephyr",
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.abi_version = 0,
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},
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.flags = 0,
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};
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#define NUM_WINDOWS 2
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static const struct adsp_ipc_window sram_window = {
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.ext_hdr = {
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.hdr.cmd = ADSP_IPC_FW_READY,
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.hdr.size = sizeof(struct adsp_ipc_window) +
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sizeof(struct adsp_ipc_window_elem) * NUM_WINDOWS,
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.type = ADSP_IPC_EXT_WINDOW,
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},
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.num_windows = NUM_WINDOWS,
|
||||
.window = {
|
||||
{
|
||||
.type = ADSP_IPC_REGION_REGS,
|
||||
.id = 0, /* map to host window 0 */
|
||||
.flags = 0,
|
||||
.size = MAILBOX_SW_REG_SIZE,
|
||||
.offset = 0,
|
||||
},
|
||||
{
|
||||
.type = ADSP_IPC_REGION_TRACE,
|
||||
.id = 3, /* map to host window 3 */
|
||||
.flags = 0,
|
||||
.size = MAILBOX_TRACE_SIZE,
|
||||
.offset = 0,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Sets up the host windows so that the host can see the memory
|
||||
* content on the DSP SRAM.
|
||||
*/
|
||||
static void prepare_host_windows(void)
|
||||
{
|
||||
/* window0, for fw status */
|
||||
sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
|
||||
sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
|
||||
DMWBA(0));
|
||||
memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
|
||||
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
|
||||
SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
|
||||
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
|
||||
|
||||
/* window3, for trace
|
||||
* zeroed by trace initialization
|
||||
*/
|
||||
sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
|
||||
sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
|
||||
DMWBA(3));
|
||||
memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
|
||||
SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Sends the firmware ready message so the firmware loader can
|
||||
* map the host windows.
|
||||
*/
|
||||
static void send_fw_ready(void)
|
||||
{
|
||||
memcpy((void *)MAILBOX_DSPBOX_BASE,
|
||||
&fw_ready_apl, sizeof(fw_ready_apl));
|
||||
|
||||
memcpy((void *)(MAILBOX_DSPBOX_BASE + sizeof(fw_ready_apl)),
|
||||
&sram_window, sizeof(sram_window));
|
||||
|
||||
SOC_DCACHE_FLUSH((void *)MAILBOX_DSPBOX_BASE, MAILBOX_DSPBOX_SIZE);
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
|
||||
sys_write32(SRAM_WINDOW_HOST_OFFSET(0) >> 12,
|
||||
IPC_HOST_BASE + IPC_DIPCIE);
|
||||
sys_write32(0x80000000 | ADSP_IPC_FW_READY,
|
||||
IPC_HOST_BASE + IPC_DIPCI);
|
||||
#else
|
||||
sys_write32(SRAM_WINDOW_HOST_OFFSET(0) >> 12,
|
||||
IPC_HOST_BASE + IPC_DIPCIDD);
|
||||
sys_write32(0x80000000 | ADSP_IPC_FW_READY,
|
||||
IPC_HOST_BASE + IPC_DIPCIDR);
|
||||
#endif
|
||||
}
|
||||
|
||||
static int adsp_init(const struct device *dev)
|
||||
{
|
||||
prepare_host_windows();
|
||||
|
||||
send_fw_ready();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Init after IPM initialization and before logging (uses memory windows) */
|
||||
SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
30
soc/xtensa/intel_adsp/common/bootloader.cmake
Normal file
30
soc/xtensa/intel_adsp/common/bootloader.cmake
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
# Copyright (c) 2019 Intel Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
set(SOC_FAMILY intel_adsp)
|
||||
|
||||
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/bootloader/CMakeLists.txt)
|
||||
if(USING_OUT_OF_TREE_BOARD)
|
||||
set(build_dir boards/${ARCH}/${BOARD}/bootloader)
|
||||
else()
|
||||
unset(build_dir)
|
||||
endif()
|
||||
|
||||
add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/bootloader ${build_dir})
|
||||
endif()
|
||||
|
||||
add_custom_target(
|
||||
process_elf ALL
|
||||
DEPENDS base_module
|
||||
DEPENDS ${ZEPHYR_FINAL_EXECUTABLE}
|
||||
COMMAND ${CMAKE_OBJCOPY} --dump-section .data=mod-apl.bin $<TARGET_FILE:base_module>
|
||||
COMMAND ${CMAKE_OBJCOPY} --add-section .module=mod-apl.bin --set-section-flags .module=load,readonly ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}.mod
|
||||
)
|
||||
|
||||
add_custom_target(
|
||||
process_bootloader ALL
|
||||
DEPENDS bootloader boot_module
|
||||
COMMAND ${CMAKE_OBJCOPY} --dump-section .data=mod-boot.bin $<TARGET_FILE:boot_module>
|
||||
COMMAND ${CMAKE_OBJCOPY} --add-section .module=mod-boot.bin --set-section-flags .module=load,readonly $<TARGET_FILE:bootloader> ${CMAKE_BINARY_DIR}/zephyr/bootloader.elf.mod
|
||||
)
|
||||
82
soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
Normal file
82
soc/xtensa/intel_adsp/common/bootloader/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
# Copyright (c) 2019 Intel Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
# TODO: Need to unbind SOF module.
|
||||
|
||||
add_library(base_module base_module.c)
|
||||
target_include_directories(base_module PUBLIC
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/include
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/../common/include
|
||||
${ZEPHYR_BASE}/../modules/hal/xtensa/include
|
||||
${ZEPHYR_BASE}/build/zephyr/include/generated
|
||||
${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
|
||||
)
|
||||
|
||||
add_library(boot_module boot_module.c)
|
||||
target_include_directories(boot_module PUBLIC
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/include
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/../common/include
|
||||
${ZEPHYR_BASE}/../modules/hal/xtensa/include
|
||||
${ZEPHYR_BASE}/build/zephyr/include/generated
|
||||
${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
|
||||
)
|
||||
|
||||
add_executable(bootloader
|
||||
boot_entry.S
|
||||
${ARCH_DIR}/${ARCH}/core/startup/memctl_default.S
|
||||
${ARCH_DIR}/${ARCH}/core/startup/memerror-vector.S
|
||||
${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S
|
||||
boot_loader.c
|
||||
start_address.S
|
||||
)
|
||||
|
||||
add_dependencies(bootloader ${SYSCALL_LIST_H_TARGET})
|
||||
|
||||
set(zephyr_sdk $ENV{ZEPHYR_SDK_INSTALL_DIR})
|
||||
|
||||
target_include_directories(bootloader PUBLIC
|
||||
./
|
||||
${ZEPHYR_BASE}/include
|
||||
${TOOLCHAIN_INCLUDES}
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/
|
||||
${SOC_DIR}/${ARCH}/${SOC_PATH}/include
|
||||
${ZEPHYR_BASE}/build/zephyr/include/generated
|
||||
${ZEPHYR_BASE}/../modules/audio/sof/zephyr/include
|
||||
)
|
||||
|
||||
# TODO: pre-process linker script. How do we use toplevel infrastructure ??
|
||||
set(bootloader_linker_script "boot_ldr")
|
||||
add_custom_command(TARGET bootloader
|
||||
PRE_LINK
|
||||
DEPENDS ${bootloader_linker_script}.x
|
||||
COMMENT "Generating Bootloader!!!!!!!"
|
||||
COMMAND ${CMAKE_C_COMPILER}
|
||||
-x assembler-with-cpp
|
||||
${NOSYSDEF_CFLAG}
|
||||
-MD
|
||||
-D_LINKER
|
||||
-D_ASMLANGUAGE
|
||||
-I ${SOC_DIR}/${ARCH}/${SOC_PATH}/include
|
||||
-I ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/include
|
||||
${current_defines}
|
||||
${linker_pass_define}
|
||||
-E ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/bootloader/${bootloader_linker_script}.x
|
||||
-P # Prevent generation of debug `#line' directives.
|
||||
-o ${bootloader_linker_script}.ld
|
||||
VERBATIM
|
||||
WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
|
||||
)
|
||||
|
||||
set_source_files_properties(boot_entry.S PROPERTIES COMPILE_FLAGS -DASSEMBLY)
|
||||
set_source_files_properties(${ARCH_DIR}/${ARCH}/core/startup/reset-vector.S PROPERTIES COMPILE_FLAGS -DBOOTLOADER)
|
||||
|
||||
target_compile_options(bootloader PUBLIC -fno-inline-functions -mlongcalls -mtext-section-literals -imacros${CMAKE_BINARY_DIR}/zephyr/include/generated/autoconf.h)
|
||||
|
||||
target_link_libraries(bootloader PUBLIC -Wl,--no-check-sections -ucall_user_start -Wl,-static -nostdlib)
|
||||
target_link_libraries(bootloader PRIVATE -T${CMAKE_BINARY_DIR}/zephyr/${bootloader_linker_script}.ld)
|
||||
|
||||
if(CONFIG_XTENSA_HAL)
|
||||
target_link_libraries(bootloader PRIVATE XTENSA_HAL)
|
||||
target_link_libraries(bootloader PRIVATE modules_xtensa_hal)
|
||||
endif()
|
||||
32
soc/xtensa/intel_adsp/common/bootloader/base_module.c
Normal file
32
soc/xtensa/intel_adsp/common/bootloader/base_module.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright(c) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include "manifest.h"
|
||||
#include <soc/memory.h>
|
||||
|
||||
/*
|
||||
* Each module has an entry in the FW manifest header. This is NOT part of
|
||||
* the SOF executable image but is inserted by object copy as a ELF section
|
||||
* for parsing by rimage (to genrate the manifest).
|
||||
*/
|
||||
struct sof_man_module_manifest apl_manifest = {
|
||||
.module = {
|
||||
.name = "BASEFW",
|
||||
.uuid = {0x2e, 0x9e, 0x86, 0xfc, 0xf8, 0x45, 0x45, 0x40,
|
||||
0xa4, 0x16, 0x89, 0x88, 0x0a, 0xe3, 0x20, 0xa9},
|
||||
.entry_point = SOF_TEXT_START,
|
||||
.type = {
|
||||
.load_type = SOF_MAN_MOD_TYPE_MODULE,
|
||||
.domain_ll = 1,
|
||||
},
|
||||
.affinity_mask = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* not used, but stops linker complaining */
|
||||
int _start;
|
||||
224
soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
Normal file
224
soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Copyright(c) 2016 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Entry point from ROM - assumes :-
|
||||
*
|
||||
* 1) C runtime environment is initialized by ROM.
|
||||
* 2) Stack is in first HPSRAM bank.
|
||||
*/
|
||||
|
||||
#include <soc/shim.h>
|
||||
#include <soc/platform.h>
|
||||
#include <soc/memory.h>
|
||||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/core-isa.h>
|
||||
|
||||
.type boot_master_core, @function
|
||||
|
||||
.begin literal_prefix .boot_entry
|
||||
.section .boot_entry.text, "ax"
|
||||
|
||||
.align 4
|
||||
.global boot_entry
|
||||
|
||||
boot_entry:
|
||||
entry a1, 48
|
||||
j boot_init
|
||||
|
||||
.align 4
|
||||
.literal_position
|
||||
#if defined(PLATFORM_RESET_MHE_AT_BOOT)
|
||||
l2_mecs:
|
||||
.word SHIM_L2_MECS
|
||||
#endif
|
||||
|
||||
#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
|
||||
l2_cache_pref:
|
||||
.word SHIM_L2_PREF_CFG
|
||||
#endif
|
||||
|
||||
sof_stack_base:
|
||||
.word SOF_STACK_BASE
|
||||
|
||||
wnd0_base:
|
||||
.word DMWBA(0)
|
||||
|
||||
wnd0_size:
|
||||
.word DMWLO(0)
|
||||
|
||||
wnd0_base_val:
|
||||
.word HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE
|
||||
|
||||
wnd0_size_val:
|
||||
.word HP_SRAM_WIN0_SIZE | 0x7
|
||||
|
||||
wnd0_status_address:
|
||||
.word HP_SRAM_WIN0_BASE
|
||||
|
||||
wnd0_error_address:
|
||||
.word HP_SRAM_WIN0_BASE | 0x4
|
||||
|
||||
#if defined(PLATFORM_MEM_INIT_AT_BOOT)
|
||||
shim_ldoctl_address:
|
||||
.word SHIM_BASE + SHIM_LDOCTL
|
||||
|
||||
ldoctl_hpsram_ldo_on:
|
||||
.word SHIM_LDOCTL_HPSRAM_LDO_ON
|
||||
|
||||
ldoctl_hpsram_ldo_bypass:
|
||||
.word SHIM_LDOCTL_HPSRAM_LDO_BYPASS
|
||||
|
||||
hspgctl0_address:
|
||||
.word HSPGCTL0
|
||||
|
||||
hsrmctl0_address:
|
||||
.word HSRMCTL0
|
||||
|
||||
hspgctl1_address:
|
||||
.word HSPGCTL1
|
||||
|
||||
hsrmctl1_address:
|
||||
.word HSRMCTL1
|
||||
|
||||
hspgists0_address:
|
||||
.word HSPGISTS0
|
||||
|
||||
hspgists1_address:
|
||||
.word HSPGISTS1
|
||||
#endif
|
||||
|
||||
fw_loaded_status_value:
|
||||
.word 0x00000005
|
||||
|
||||
fw_no_errors_value:
|
||||
.word 0x00000000
|
||||
|
||||
boot_init:
|
||||
.align 4
|
||||
#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT)
|
||||
l32r a3, l2_cache_pref
|
||||
movi a5, 0
|
||||
s32i a5, a3, 0
|
||||
memw
|
||||
#endif
|
||||
|
||||
#if defined(PLATFORM_RESET_MHE_AT_BOOT)
|
||||
/* reset memory hole */
|
||||
l32r a3, l2_mecs
|
||||
movi a5, 0
|
||||
s32i a5, a3, 0
|
||||
#endif
|
||||
|
||||
#if defined(PLATFORM_MEM_INIT_AT_BOOT)
|
||||
/* turn on memory _before_ stack reprogramming */
|
||||
|
||||
l32r a3, ldoctl_hpsram_ldo_on
|
||||
l32r a5, shim_ldoctl_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
|
||||
/* delay for 256 iterations before touching pwr regs */
|
||||
movi a2, 256
|
||||
1: addi.n a2, a2, -1
|
||||
bnez a2, 1b
|
||||
|
||||
movi a3, 0
|
||||
l32r a5, hspgctl0_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
|
||||
l32r a5, hsrmctl0_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
|
||||
l32r a5, hspgctl1_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
|
||||
l32r a5, hsrmctl1_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
|
||||
/* wait for status of first bank group */
|
||||
l32r a5, hspgists0_address
|
||||
2:
|
||||
l32i a3, a5, 0
|
||||
bnez a3, 2b
|
||||
|
||||
/* wait for status of second bank group */
|
||||
l32r a5, hspgists1_address
|
||||
3:
|
||||
l32i a3, a5, 0
|
||||
bnez a3, 3b
|
||||
|
||||
/* delay for 256 iterations before touching pwr regs */
|
||||
movi a2, 256
|
||||
4: addi.n a2, a2, -1
|
||||
bnez a2, 4b
|
||||
|
||||
l32r a3, ldoctl_hpsram_ldo_bypass
|
||||
l32r a5, shim_ldoctl_address
|
||||
s32i a3, a5, 0
|
||||
memw
|
||||
#endif
|
||||
|
||||
/* reprogram stack to the area defined by main FW */
|
||||
l32r a3, sof_stack_base
|
||||
mov sp, a3
|
||||
|
||||
/* set status register to 0x00000005 in wnd0 */
|
||||
l32r a3, fw_loaded_status_value
|
||||
l32r a5, wnd0_status_address
|
||||
s32i a3, a5, 0
|
||||
|
||||
/* set error register to 0x00 in wnd0 */
|
||||
l32r a3, fw_no_errors_value
|
||||
l32r a5, wnd0_error_address
|
||||
s32i a3, a5, 0
|
||||
|
||||
/* realloc memory window0 to
|
||||
continue reporting boot progress */
|
||||
l32r a3, wnd0_size
|
||||
l32r a5, wnd0_size_val
|
||||
s32i a5, a3, 0
|
||||
memw
|
||||
l32r a3, wnd0_base
|
||||
l32r a5, wnd0_base_val
|
||||
s32i a5, a3, 0
|
||||
memw
|
||||
|
||||
#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \
|
||||
XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
|
||||
/* Enable zero-overhead loop instr buffer,
|
||||
and snoop responses, if configured. */
|
||||
movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN)
|
||||
rsr a2, MEMCTL
|
||||
or a2, a2, a3
|
||||
wsr a2, MEMCTL
|
||||
#endif
|
||||
|
||||
/* determine core we are running on */
|
||||
rsr.prid a2
|
||||
movi a3, PLATFORM_PRIMARY_CORE_ID
|
||||
beq a2, a3, 1f
|
||||
|
||||
/* no core should get here */
|
||||
j dead
|
||||
|
||||
1:
|
||||
/* we are primary core so boot it */
|
||||
call8 boot_master_core
|
||||
|
||||
dead:
|
||||
/* should never get here - we are dead */
|
||||
j dead
|
||||
|
||||
.size boot_entry, . - boot_entry
|
||||
|
||||
.end literal_prefix
|
||||
213
soc/xtensa/intel_adsp/common/bootloader/boot_ldr.x
Normal file
213
soc/xtensa/intel_adsp/common/bootloader/boot_ldr.x
Normal file
|
|
@ -0,0 +1,213 @@
|
|||
OUTPUT_ARCH(xtensa)
|
||||
|
||||
#include <soc/memory.h>
|
||||
|
||||
PROVIDE(__memctl_default = 0x00000000);
|
||||
PROVIDE(_MemErrorHandler = 0x00000000);
|
||||
MEMORY
|
||||
{
|
||||
boot_entry_text :
|
||||
org = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
|
||||
len = IMR_BOOT_LDR_TEXT_ENTRY_SIZE
|
||||
boot_entry_lit :
|
||||
org = IMR_BOOT_LDR_LIT_BASE,
|
||||
len = IMR_BOOT_LDR_LIT_SIZE
|
||||
sof_text :
|
||||
org = IMR_BOOT_LDR_TEXT_BASE,
|
||||
len = IMR_BOOT_LDR_TEXT_SIZE,
|
||||
sof_data :
|
||||
org = IMR_BOOT_LDR_DATA_BASE,
|
||||
len = IMR_BOOT_LDR_DATA_SIZE
|
||||
sof_bss_data :
|
||||
org = IMR_BOOT_LDR_BSS_BASE,
|
||||
len = IMR_BOOT_LDR_BSS_SIZE
|
||||
sof_stack :
|
||||
org = BOOT_LDR_STACK_BASE,
|
||||
len = BOOT_LDR_STACK_SIZE
|
||||
wnd0 :
|
||||
org = HP_SRAM_WIN0_BASE,
|
||||
len = HP_SRAM_WIN0_SIZE
|
||||
}
|
||||
PHDRS
|
||||
{
|
||||
boot_entry_text_phdr PT_LOAD;
|
||||
boot_entry_lit_phdr PT_LOAD;
|
||||
sof_text_phdr PT_LOAD;
|
||||
sof_data_phdr PT_LOAD;
|
||||
sof_bss_data_phdr PT_LOAD;
|
||||
sof_stack_phdr PT_LOAD;
|
||||
wnd0_phdr PT_LOAD;
|
||||
}
|
||||
ENTRY(boot_entry)
|
||||
EXTERN(reset_vector)
|
||||
SECTIONS
|
||||
{
|
||||
.boot_entry.text : ALIGN(4)
|
||||
{
|
||||
_boot_entry_text_start = ABSOLUTE(.);
|
||||
KEEP (*(.boot_entry.text))
|
||||
_boot_entry_text_end = ABSOLUTE(.);
|
||||
} >boot_entry_text :boot_entry_text_phdr
|
||||
.boot_entry.literal : ALIGN(4)
|
||||
{
|
||||
_boot_entry_literal_start = ABSOLUTE(.);
|
||||
*(.boot_entry.literal)
|
||||
*(.literal .literal.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||||
_boot_entry_literal_end = ABSOLUTE(.);
|
||||
} >boot_entry_lit :boot_entry_lit_phdr
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
_stext = .;
|
||||
_text_start = ABSOLUTE(.);
|
||||
*(.entry.text)
|
||||
*(.init.literal)
|
||||
KEEP(*(.init))
|
||||
*( .text .text.*)
|
||||
*(.fini.literal)
|
||||
KEEP(*(.fini))
|
||||
*(.gnu.version)
|
||||
KEEP (*(.ResetVector.text))
|
||||
KEEP (*(.ResetHandler.text))
|
||||
_text_end = ABSOLUTE(.);
|
||||
_etext = .;
|
||||
} >sof_text :sof_text_phdr
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
_rodata_start = ABSOLUTE(.);
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||
KEEP (*(.xt_except_table))
|
||||
KEEP (*(.gcc_except_table))
|
||||
*(.gnu.linkonce.e.*)
|
||||
*(.gnu.version_r)
|
||||
KEEP (*(.eh_frame))
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc)
|
||||
*(.gnu.linkonce.h.*)
|
||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||
*(.xt_except_desc_end)
|
||||
*(.dynamic)
|
||||
*(.gnu.version_d)
|
||||
. = ALIGN(4);
|
||||
_bss_table_start = ABSOLUTE(.);
|
||||
LONG(_bss_start)
|
||||
LONG(_bss_end)
|
||||
_bss_table_end = ABSOLUTE(.);
|
||||
_rodata_end = ABSOLUTE(.);
|
||||
} >sof_data :sof_data_phdr
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
_data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP(*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
KEEP(*(.jcr))
|
||||
_data_end = ABSOLUTE(.);
|
||||
} >sof_data :sof_data_phdr
|
||||
.lit4 : ALIGN(4)
|
||||
{
|
||||
_lit4_start = ABSOLUTE(.);
|
||||
*(*.lit4)
|
||||
*(.lit4.*)
|
||||
*(.gnu.linkonce.lit4.*)
|
||||
_lit4_end = ABSOLUTE(.);
|
||||
} >sof_data :sof_data_phdr
|
||||
.bss (NOLOAD) : ALIGN(8)
|
||||
{
|
||||
. = ALIGN (8);
|
||||
_bss_start = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.sbss2)
|
||||
*(.sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (8);
|
||||
_bss_end = ABSOLUTE(.);
|
||||
} >sof_bss_data :sof_bss_data_phdr
|
||||
_man = 0x1234567;
|
||||
PROVIDE(_memmap_vecbase_reset = (((((((0xBE000000 + 0x8000) + 0x2000) + 0x800) + 0x800) + 0x1000) + 0x2000) + (0x1000 + 0x1000)));
|
||||
_memmap_cacheattr_wbna_trapnull = 0xFF42FFF2;
|
||||
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wbna_trapnull);
|
||||
__stack = 0xBE000000 + (1 * 0x1000);
|
||||
__wnd0 = ((((((0xBE000000 + 0x8000) + 0x2000) + 0x800) + 0x800) + 0x1000) + 0x2000);
|
||||
__wnd0_size = (0x1000 + 0x1000);
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
.xtensa.info 0 : { *(.xtensa.info) }
|
||||
.xt.insn 0 :
|
||||
{
|
||||
KEEP (*(.xt.insn))
|
||||
KEEP (*(.gnu.linkonce.x.*))
|
||||
}
|
||||
.xt.prop 0 :
|
||||
{
|
||||
KEEP (*(.xt.prop))
|
||||
KEEP (*(.xt.prop.*))
|
||||
KEEP (*(.gnu.linkonce.prop.*))
|
||||
}
|
||||
.xt.lit 0 :
|
||||
{
|
||||
KEEP (*(.xt.lit))
|
||||
KEEP (*(.xt.lit.*))
|
||||
KEEP (*(.gnu.linkonce.p.*))
|
||||
}
|
||||
.xt.profile_range 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_range))
|
||||
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||
}
|
||||
.xt.profile_ranges 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_ranges))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||
}
|
||||
.xt.profile_files 0 :
|
||||
{
|
||||
KEEP (*(.xt.profile_files))
|
||||
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||
}
|
||||
}
|
||||
347
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
Normal file
347
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
Normal file
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* Copyright(c) 2016 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <cavs/version.h>
|
||||
|
||||
#include <soc/platform.h>
|
||||
#include <soc/memory.h>
|
||||
#include <soc/shim.h>
|
||||
#include <adsp/io.h>
|
||||
#include <soc.h>
|
||||
#include "manifest.h"
|
||||
|
||||
#if CONFIG_SOC_INTEL_S1000
|
||||
#define MANIFEST_BASE BOOT_LDR_MANIFEST_BASE
|
||||
#else
|
||||
#define MANIFEST_BASE IMR_BOOT_LDR_MANIFEST_BASE
|
||||
#endif
|
||||
|
||||
extern void __start(void);
|
||||
|
||||
#if !defined(CONFIG_SOC_INTEL_S1000)
|
||||
#define MANIFEST_SEGMENT_COUNT 3
|
||||
|
||||
static inline void idelay(int n)
|
||||
{
|
||||
while (n--) {
|
||||
__asm__ volatile("nop");
|
||||
}
|
||||
}
|
||||
|
||||
/* generic string compare cloned into the bootloader to
|
||||
* compact code and make it more readable
|
||||
*/
|
||||
int strcmp(const char *s1, const char *s2)
|
||||
{
|
||||
while (*s1 != 0 && *s2 != 0) {
|
||||
if (*s1 < *s2)
|
||||
return -1;
|
||||
if (*s1 > *s2)
|
||||
return 1;
|
||||
s1++;
|
||||
s2++;
|
||||
}
|
||||
|
||||
/* did both string end */
|
||||
if (*s1 != 0)
|
||||
return 1;
|
||||
if (*s2 != 0)
|
||||
return -1;
|
||||
|
||||
/* match */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* memcopy used by boot loader */
|
||||
static inline void bmemcpy(void *dest, void *src, size_t bytes)
|
||||
{
|
||||
uint32_t *d = dest;
|
||||
uint32_t *s = src;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < (bytes >> 2); i++)
|
||||
d[i] = s[i];
|
||||
|
||||
SOC_DCACHE_FLUSH(dest, bytes);
|
||||
}
|
||||
|
||||
/* bzero used by bootloader */
|
||||
static inline void bbzero(void *dest, size_t bytes)
|
||||
{
|
||||
uint32_t *d = dest;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < (bytes >> 2); i++)
|
||||
d[i] = 0;
|
||||
|
||||
SOC_DCACHE_FLUSH(dest, bytes);
|
||||
}
|
||||
|
||||
static void parse_module(struct sof_man_fw_header *hdr,
|
||||
struct sof_man_module *mod)
|
||||
{
|
||||
int i;
|
||||
uint32_t bias;
|
||||
|
||||
/* each module has 3 segments */
|
||||
for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) {
|
||||
|
||||
switch (mod->segment[i].flags.r.type) {
|
||||
case SOF_MAN_SEGMENT_TEXT:
|
||||
case SOF_MAN_SEGMENT_DATA:
|
||||
bias = (mod->segment[i].file_offset -
|
||||
SOF_MAN_ELF_TEXT_OFFSET);
|
||||
|
||||
/* copy from IMR to SRAM */
|
||||
bmemcpy((void *)mod->segment[i].v_base_addr,
|
||||
(void *)((int)hdr + bias),
|
||||
mod->segment[i].flags.r.length *
|
||||
HOST_PAGE_SIZE);
|
||||
break;
|
||||
case SOF_MAN_SEGMENT_BSS:
|
||||
/* copy from IMR to SRAM */
|
||||
bbzero((void *)mod->segment[i].v_base_addr,
|
||||
mod->segment[i].flags.r.length *
|
||||
HOST_PAGE_SIZE);
|
||||
break;
|
||||
default:
|
||||
/* ignore */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* On Sue Creek the boot loader is attached separately, no need to skip it */
|
||||
#if CONFIG_SOC_INTEL_S1000
|
||||
#define MAN_SKIP_ENTRIES 0
|
||||
#else
|
||||
#define MAN_SKIP_ENTRIES 1
|
||||
#endif
|
||||
|
||||
static uint32_t get_fw_size_in_use(void)
|
||||
{
|
||||
struct sof_man_fw_desc *desc =
|
||||
(struct sof_man_fw_desc *)MANIFEST_BASE;
|
||||
struct sof_man_fw_header *hdr = &desc->header;
|
||||
struct sof_man_module *mod;
|
||||
uint32_t fw_size_in_use = 0xffffffff;
|
||||
int i;
|
||||
|
||||
/* Calculate fw size passed in BASEFW module in MANIFEST */
|
||||
for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
|
||||
mod = (struct sof_man_module *)((char *)desc +
|
||||
SOF_MAN_MODULE_OFFSET(i));
|
||||
if (strcmp((char *)mod->name, "BASEFW"))
|
||||
continue;
|
||||
for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) {
|
||||
if (mod->segment[i].flags.r.type
|
||||
== SOF_MAN_SEGMENT_BSS) {
|
||||
fw_size_in_use = mod->segment[i].v_base_addr
|
||||
- HP_SRAM_BASE
|
||||
+ (mod->segment[i].flags.r.length
|
||||
* HOST_PAGE_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return fw_size_in_use;
|
||||
}
|
||||
|
||||
/* parse FW manifest and copy modules */
|
||||
static void parse_manifest(void)
|
||||
{
|
||||
struct sof_man_fw_desc *desc =
|
||||
(struct sof_man_fw_desc *)MANIFEST_BASE;
|
||||
struct sof_man_fw_header *hdr = &desc->header;
|
||||
struct sof_man_module *mod;
|
||||
int i;
|
||||
|
||||
/* copy module to SRAM - skip bootloader module */
|
||||
for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
|
||||
|
||||
mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
|
||||
parse_module(hdr, mod);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CAVS_VERSION >= CAVS_VERSION_1_8
|
||||
/* function powers up a number of memory banks provided as an argument and
|
||||
* gates remaining memory banks
|
||||
*/
|
||||
static int32_t hp_sram_pm_banks(uint32_t banks)
|
||||
{
|
||||
int delay_count = 256;
|
||||
uint32_t status;
|
||||
uint32_t ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1;
|
||||
uint32_t total_banks_count = PLATFORM_HPSRAM_EBB_COUNT;
|
||||
|
||||
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON);
|
||||
|
||||
/* add some delay before touch power register */
|
||||
idelay(delay_count);
|
||||
|
||||
/* bit masks reflect total number of available EBB (banks) in each
|
||||
* segment; current implementation supports 2 segments 0,1
|
||||
*/
|
||||
if (total_banks_count > EBB_SEGMENT_SIZE) {
|
||||
ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
|
||||
ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
|
||||
EBB_SEGMENT_SIZE - 1, 0);
|
||||
} else{
|
||||
ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1,
|
||||
0);
|
||||
ebb_avail_mask1 = 0;
|
||||
}
|
||||
|
||||
/* bit masks of banks that have to be powered up in each segment */
|
||||
if (banks > EBB_SEGMENT_SIZE) {
|
||||
ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
|
||||
ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
|
||||
0);
|
||||
} else{
|
||||
/* assumption that ebb_in_use is > 0 */
|
||||
ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0);
|
||||
ebb_mask1 = 0;
|
||||
}
|
||||
|
||||
/* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */
|
||||
io_reg_write(HSPGCTL0, (~ebb_mask0) & ebb_avail_mask0);
|
||||
io_reg_write(HSRMCTL0, (~ebb_mask0) & ebb_avail_mask0);
|
||||
io_reg_write(HSPGCTL1, (~ebb_mask1) & ebb_avail_mask1);
|
||||
io_reg_write(HSRMCTL1, (~ebb_mask1) & ebb_avail_mask1);
|
||||
|
||||
/* query the power status of first part of HP memory */
|
||||
/* to check whether it has been powered up. A few */
|
||||
/* cycles are needed for it to be powered up */
|
||||
status = io_reg_read(HSPGISTS0);
|
||||
while (status != ((~ebb_mask0) & ebb_avail_mask0)) {
|
||||
idelay(delay_count);
|
||||
status = io_reg_read(HSPGISTS0);
|
||||
}
|
||||
/* query the power status of second part of HP memory */
|
||||
/* and do as above code */
|
||||
|
||||
status = io_reg_read(HSPGISTS1);
|
||||
while (status != ((~ebb_mask1) & ebb_avail_mask1)) {
|
||||
idelay(delay_count);
|
||||
status = io_reg_read(HSPGISTS1);
|
||||
}
|
||||
/* add some delay before touch power register */
|
||||
idelay(delay_count);
|
||||
|
||||
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t hp_sram_power_on_memory(uint32_t memory_size)
|
||||
{
|
||||
uint32_t ebb_in_use;
|
||||
|
||||
/* calculate total number of used SRAM banks (EBB)
|
||||
* to power up only necessary banks
|
||||
*/
|
||||
ebb_in_use = (!(memory_size % SRAM_BANK_SIZE)) ?
|
||||
(memory_size / SRAM_BANK_SIZE) :
|
||||
(memory_size / SRAM_BANK_SIZE) + 1;
|
||||
|
||||
return hp_sram_pm_banks(ebb_in_use);
|
||||
}
|
||||
|
||||
static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
|
||||
{
|
||||
/* keep enabled only memory banks used by FW */
|
||||
return hp_sram_power_on_memory(memory_size);
|
||||
}
|
||||
|
||||
static int32_t hp_sram_init(void)
|
||||
{
|
||||
return hp_sram_power_on_memory(HP_SRAM_SIZE);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t hp_sram_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static int32_t lp_sram_init(void)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t lspgctl_value;
|
||||
uint32_t timeout_counter, delay_count = 256;
|
||||
|
||||
timeout_counter = delay_count;
|
||||
|
||||
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON);
|
||||
|
||||
/* add some delay before writing power registers */
|
||||
idelay(delay_count);
|
||||
|
||||
lspgctl_value = shim_read(SHIM_LSPGISTS);
|
||||
shim_write(SHIM_LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0));
|
||||
|
||||
/* add some delay before checking the status */
|
||||
idelay(delay_count);
|
||||
|
||||
/* query the power status of first part of LP memory */
|
||||
/* to check whether it has been powered up. A few */
|
||||
/* cycles are needed for it to be powered up */
|
||||
status = io_reg_read(LSPGISTS);
|
||||
while (status) {
|
||||
if (!timeout_counter--) {
|
||||
break;
|
||||
}
|
||||
idelay(delay_count);
|
||||
status = io_reg_read(LSPGISTS);
|
||||
}
|
||||
|
||||
shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* boot master core */
|
||||
void boot_master_core(void)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
|
||||
/* init the HPSRAM */
|
||||
result = hp_sram_init();
|
||||
if (result < 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* init the LPSRAM */
|
||||
|
||||
result = lp_sram_init();
|
||||
if (result < 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SOC_INTEL_S1000)
|
||||
/* parse manifest and copy modules */
|
||||
parse_manifest();
|
||||
|
||||
hp_sram_power_off_unused_banks(get_fw_size_in_use());
|
||||
#endif
|
||||
/* now call SOF entry */
|
||||
__start();
|
||||
}
|
||||
34
soc/xtensa/intel_adsp/common/bootloader/boot_module.c
Normal file
34
soc/xtensa/intel_adsp/common/bootloader/boot_module.c
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright(c) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Marcin Maka <marcin.maka@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include "manifest.h"
|
||||
#include <soc/memory.h>
|
||||
|
||||
/*
|
||||
* Each module has an entry in the FW manifest header. This is NOT part of
|
||||
* the SOF executable image but is inserted by object copy as a ELF section
|
||||
* for parsing by rimage (to generate the manifest).
|
||||
*/
|
||||
struct sof_man_module_manifest apl_bootldr_manifest = {
|
||||
.module = {
|
||||
.name = "BRNGUP",
|
||||
.uuid = {
|
||||
0xcc, 0x48, 0x7b, 0x0d, 0xa9, 0x1e, 0x0a, 0x47,
|
||||
0xa8, 0xc1, 0x53, 0x34, 0x24, 0x52, 0x8a, 0x17
|
||||
},
|
||||
.entry_point = IMR_BOOT_LDR_TEXT_ENTRY_BASE,
|
||||
.type = {
|
||||
.load_type = SOF_MAN_MOD_TYPE_MODULE,
|
||||
.domain_ll = 1,
|
||||
},
|
||||
.affinity_mask = 3,
|
||||
},
|
||||
};
|
||||
|
||||
/* not used, but stops linker complaining */
|
||||
int _start;
|
||||
199
soc/xtensa/intel_adsp/common/bootloader/manifest.h
Normal file
199
soc/xtensa/intel_adsp/common/bootloader/manifest.h
Normal file
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* Copyright(c) 2017 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_UAPI_USER_MANIFEST_H__
|
||||
#define __INCLUDE_UAPI_USER_MANIFEST_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* start offset for base FW module */
|
||||
#define SOF_MAN_ELF_TEXT_OFFSET 0x2000
|
||||
|
||||
/* FW Extended Manifest Header id = $AE1 */
|
||||
#define SOF_MAN_EXT_HEADER_MAGIC 0x31454124
|
||||
|
||||
/* module type load type */
|
||||
#define SOF_MAN_MOD_TYPE_BUILTIN 0
|
||||
#define SOF_MAN_MOD_TYPE_MODULE 1
|
||||
|
||||
struct sof_man_module_type {
|
||||
uint32_t load_type:4; /* SOF_MAN_MOD_TYPE_ */
|
||||
uint32_t auto_start:1;
|
||||
uint32_t domain_ll:1;
|
||||
uint32_t domain_dp:1;
|
||||
uint32_t rsvd_:25;
|
||||
};
|
||||
|
||||
/* segment flags.type */
|
||||
#define SOF_MAN_SEGMENT_TEXT 0
|
||||
#define SOF_MAN_SEGMENT_RODATA 1
|
||||
#define SOF_MAN_SEGMENT_DATA 1
|
||||
#define SOF_MAN_SEGMENT_BSS 2
|
||||
#define SOF_MAN_SEGMENT_EMPTY 15
|
||||
|
||||
union sof_man_segment_flags {
|
||||
uint32_t ul;
|
||||
struct {
|
||||
uint32_t contents:1;
|
||||
uint32_t alloc:1;
|
||||
uint32_t load:1;
|
||||
uint32_t readonly:1;
|
||||
uint32_t code:1;
|
||||
uint32_t data:1;
|
||||
uint32_t _rsvd0:2;
|
||||
uint32_t type:4; /* MAN_SEGMENT_ */
|
||||
uint32_t _rsvd1:4;
|
||||
uint32_t length:16; /* of segment in pages */
|
||||
} r;
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Module segment descriptor. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_segment_desc {
|
||||
union sof_man_segment_flags flags;
|
||||
uint32_t v_base_addr;
|
||||
uint32_t file_offset;
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* The firmware binary can be split into several modules.
|
||||
*/
|
||||
|
||||
#define SOF_MAN_MOD_ID_LEN 4
|
||||
#define SOF_MAN_MOD_NAME_LEN 8
|
||||
#define SOF_MAN_MOD_SHA256_LEN 32
|
||||
#define SOF_MAN_MOD_ID {'$', 'A', 'M', 'E'}
|
||||
|
||||
/*
|
||||
* Each module has an entry in the FW header. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_module {
|
||||
uint8_t struct_id[SOF_MAN_MOD_ID_LEN]; /* SOF_MAN_MOD_ID */
|
||||
uint8_t name[SOF_MAN_MOD_NAME_LEN];
|
||||
uint8_t uuid[16];
|
||||
struct sof_man_module_type type;
|
||||
uint8_t hash[SOF_MAN_MOD_SHA256_LEN];
|
||||
uint32_t entry_point;
|
||||
uint16_t cfg_offset;
|
||||
uint16_t cfg_count;
|
||||
uint32_t affinity_mask;
|
||||
uint16_t instance_max_count; /* max number of instances */
|
||||
uint16_t instance_bss_size; /* instance (pages) */
|
||||
struct sof_man_segment_desc segment[3];
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Each module has a configuration in the FW header. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_mod_config {
|
||||
uint32_t par[4]; /* module parameters */
|
||||
uint32_t is_pages; /* actual size of instance .bss (pages) */
|
||||
uint32_t cps; /* cycles per second */
|
||||
uint32_t ibs; /* input buffer size (bytes) */
|
||||
uint32_t obs; /* output buffer size (bytes) */
|
||||
uint32_t module_flags; /* flags, reserved for future use */
|
||||
uint32_t cpc; /* cycles per single run */
|
||||
uint32_t obls; /* output block size, reserved for future use */
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* FW Manifest Header
|
||||
*/
|
||||
|
||||
#define SOF_MAN_FW_HDR_FW_NAME_LEN 8
|
||||
#define SOF_MAN_FW_HDR_ID {'$', 'A', 'M', '1'}
|
||||
#define SOF_MAN_FW_HDR_NAME "ADSPFW"
|
||||
#define SOF_MAN_FW_HDR_FLAGS 0x0
|
||||
#define SOF_MAN_FW_HDR_FEATURES 0x1ff
|
||||
|
||||
/*
|
||||
* The firmware has a standard header that is checked by the ROM on firmware
|
||||
* loading. preload_page_count is used by DMA code loader and is entire
|
||||
* image size on CNL. i.e. CNL: total size of the binary’s .text and .rodata
|
||||
* Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_fw_header {
|
||||
uint8_t header_id[4];
|
||||
uint32_t header_len;
|
||||
uint8_t name[SOF_MAN_FW_HDR_FW_NAME_LEN];
|
||||
/* number of pages of preloaded image loaded by driver */
|
||||
uint32_t preload_page_count;
|
||||
uint32_t fw_image_flags;
|
||||
uint32_t feature_mask;
|
||||
uint16_t major_version;
|
||||
uint16_t minor_version;
|
||||
uint16_t hotfix_version;
|
||||
uint16_t build_version;
|
||||
uint32_t num_module_entries;
|
||||
uint32_t hw_buf_base_addr;
|
||||
uint32_t hw_buf_length;
|
||||
/* target address for binary loading as offset in IMR
|
||||
* must be == base offset
|
||||
*/
|
||||
uint32_t load_offset;
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Firmware manifest descriptor. This can contain N modules and N module
|
||||
* configs. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_fw_desc {
|
||||
struct sof_man_fw_header header;
|
||||
|
||||
/* Warning - hack for module arrays. For some unknown reason the we
|
||||
* have a variable size array of struct man_module followed by a
|
||||
* variable size array of struct mod_config. These should have been
|
||||
* merged into a variable array of a parent structure. We have to hack
|
||||
* around this in many places....
|
||||
*
|
||||
* struct sof_man_module man_module[];
|
||||
* struct sof_man_mod_config mod_config[];
|
||||
*/
|
||||
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Component Descriptor. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_component_desc {
|
||||
uint32_t reserved[2]; /* all 0 */
|
||||
uint32_t version;
|
||||
uint8_t hash[SOF_MAN_MOD_SHA256_LEN];
|
||||
uint32_t base_offset;
|
||||
uint32_t limit_offset;
|
||||
uint32_t attributes[4];
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Audio DSP extended metadata. Used by ROM - Immutable.
|
||||
*/
|
||||
struct sof_man_adsp_meta_file_ext {
|
||||
uint32_t ext_type; /* always 17 for ADSP extension */
|
||||
uint32_t ext_len;
|
||||
uint32_t imr_type;
|
||||
uint8_t reserved[16]; /* all 0 */
|
||||
struct sof_man_component_desc comp_desc[1];
|
||||
} __attribute__((packed));
|
||||
|
||||
/*
|
||||
* Module Manifest for rimage module metadata. Not used by ROM.
|
||||
*/
|
||||
struct sof_man_module_manifest {
|
||||
struct sof_man_module module;
|
||||
uint32_t text_size;
|
||||
};
|
||||
|
||||
/*
|
||||
* Module offset in manifest.
|
||||
*/
|
||||
#define SOF_MAN_MODULE_OFFSET(index) \
|
||||
(sizeof(struct sof_man_fw_header) + \
|
||||
(index) * sizeof(struct sof_man_module))
|
||||
|
||||
#endif
|
||||
11
soc/xtensa/intel_adsp/common/bootloader/start_address.S
Normal file
11
soc/xtensa/intel_adsp/common/bootloader/start_address.S
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc/memory.h>
|
||||
|
||||
.global _start
|
||||
.equ _start, SOF_TEXT_BASE
|
||||
|
||||
42
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
Executable file
42
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
Executable file
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python3
|
||||
#
|
||||
# Copyright (c) 2020 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# ADSP devices have their RAM regions mapped twice, once in the 512MB
|
||||
# region from 0x80000000-0x9fffffff and again from
|
||||
# 0xa0000000-0xbfffffff. The first mapping is set in the CPU to
|
||||
# bypass the L1 cache, and so access through pointers in that region
|
||||
# is coherent between CPUs (but slow). The second region accesses the
|
||||
# same memory through the L1 cache and requires careful flushing when
|
||||
# used with shared data.
|
||||
#
|
||||
# This distinction is exposed in the linker script, where some symbols
|
||||
# (e.g. stack regions) are linked into cached memory, but others
|
||||
# (general kernel memory) are not. But the rimage signing tool
|
||||
# doesn't understand that and fails if regions aren't contiguous.
|
||||
#
|
||||
# Walk the sections in the ELF file, changing the VMA/LMA of each
|
||||
# uncached section to the equivalent address in the cached area of
|
||||
# memory.
|
||||
|
||||
import os
|
||||
import sys
|
||||
from elftools.elf.elffile import ELFFile
|
||||
|
||||
objcopy_bin = sys.argv[1]
|
||||
elffile = sys.argv[2]
|
||||
|
||||
fixup =[]
|
||||
with open(elffile, "rb") as fd:
|
||||
elf = ELFFile(fd)
|
||||
for s in elf.iter_sections():
|
||||
addr = s.header.sh_addr
|
||||
if addr >= 0x80000000 and addr < 0xa0000000:
|
||||
print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
|
||||
fixup.append(s.name)
|
||||
|
||||
for s in fixup:
|
||||
cmd = f"{objcopy_bin} --change-section-address {s}+0x20000000 {elffile}"
|
||||
print(cmd)
|
||||
os.system(cmd)
|
||||
18
soc/xtensa/intel_adsp/common/include/adsp/cache.h
Normal file
18
soc/xtensa/intel_adsp/common/include/adsp/cache.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
|
||||
/* macros for data cache operations */
|
||||
#define SOC_DCACHE_FLUSH(addr, size) \
|
||||
xthal_dcache_region_writeback((addr), (size))
|
||||
#define SOC_DCACHE_INVALIDATE(addr, size) \
|
||||
xthal_dcache_region_invalidate((addr), (size))
|
||||
|
||||
#endif
|
||||
65
soc/xtensa/intel_adsp/common/include/adsp/io.h
Normal file
65
soc/xtensa/intel_adsp/common/include/adsp/io.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright(c) 2016 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <sys/sys_io.h>
|
||||
#include <arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
/* Note: Parameters in different order */
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask,
|
||||
uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
/* Note: Parameters in different order */
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
static inline uint32_t shim_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(SHIM_BASE + reg);
|
||||
}
|
||||
|
||||
static inline void shim_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, (SHIM_BASE + reg));
|
||||
}
|
||||
|
||||
static inline uint64_t shim_read64(uint32_t reg)
|
||||
{
|
||||
return *((volatile uint64_t*)(SHIM_BASE + reg));
|
||||
}
|
||||
|
||||
static inline void shim_write64(uint32_t reg, uint64_t val)
|
||||
{
|
||||
*((volatile uint64_t*)(SHIM_BASE + reg)) = val;
|
||||
}
|
||||
|
||||
#endif
|
||||
22
soc/xtensa/intel_adsp/common/include/cavs/cpu.h
Normal file
22
soc/xtensa/intel_adsp/common/include/cavs/cpu.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright(c) 2019 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
|
||||
*/
|
||||
|
||||
/**
|
||||
* \file cavs/lib/cpu.h
|
||||
* \brief DSP parameters, common for cAVS platforms.
|
||||
*/
|
||||
|
||||
#ifndef __CAVS_CPU_H__
|
||||
#define __CAVS_CPU_H__
|
||||
|
||||
/** \brief Number of available DSP cores (conf. by kconfig) */
|
||||
#define PLATFORM_CORE_COUNT (defined(CONFIG_SMP) ? CONFIG_MP_NUM_CPUS : 1)
|
||||
|
||||
/** Id of master DSP core */
|
||||
#define PLATFORM_PRIMARY_CORE_ID 0
|
||||
|
||||
#endif /* __CAVS_CPU_H__ */
|
||||
62
soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
Normal file
62
soc/xtensa/intel_adsp/common/include/cavs/mailbox.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright(c) 2019 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
* Keyon Jie <yang.jie@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __CAVS_MAILBOX_H__
|
||||
#define __CAVS_MAILBOX_H__
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* The Window Region on HPSRAM for cAVS platforms is organised like this :-
|
||||
* +--------------------------------------------------------------------------+
|
||||
* | Offset | Region | Size |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SRAM_TRACE_BASE | Trace Buffer W3| SRAM_TRACE_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SRAM_DEBUG_BASE | Debug data W2 | SRAM_DEBUG_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SRAM_INBOX_BASE | Inbox W1 | SRAM_INBOX_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SRAM_OUTBOX_BASE | Outbox W0 | SRAM_MAILBOX_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
* | SRAM_SW_REG_BASE | SW Registers W0| SRAM_SW_REG_SIZE |
|
||||
* +---------------------+----------------+-----------------------------------+
|
||||
*
|
||||
* Note: For suecreek SRAM_SW_REG window does not exist - MAILBOX_SW_REG_BASE
|
||||
* and MAILBOX_SW_REG_BASE are equal to 0
|
||||
*/
|
||||
|
||||
/* window 3 - trace */
|
||||
#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE
|
||||
#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE
|
||||
|
||||
/* window 2 debug, exception and stream */
|
||||
#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE
|
||||
#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE
|
||||
|
||||
#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE
|
||||
#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE
|
||||
#define MAILBOX_EXCEPTION_OFFSET SRAM_DEBUG_SIZE
|
||||
|
||||
#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE
|
||||
#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE
|
||||
#define MAILBOX_STREAM_OFFSET (SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE)
|
||||
|
||||
/* window 1 inbox/downlink and FW registers */
|
||||
#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE
|
||||
#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE
|
||||
|
||||
/* window 0 */
|
||||
#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE
|
||||
#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE
|
||||
|
||||
#define MAILBOX_SW_REG_SIZE SRAM_SW_REG_SIZE
|
||||
#define MAILBOX_SW_REG_BASE SRAM_SW_REG_BASE
|
||||
|
||||
#endif /* __CAVS_MAILBOX_H__ */
|
||||
29
soc/xtensa/intel_adsp/common/include/cavs/version.h
Normal file
29
soc/xtensa/intel_adsp/common/include/cavs/version.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright(c) 2018 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Bartosz Kokoszko <bartoszx.kokoszko@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __CAVS_VERSION_H__
|
||||
#define __CAVS_VERSION_H__
|
||||
|
||||
#include <autoconf.h>
|
||||
|
||||
#define CAVS_VERSION_1_5 0x10500
|
||||
#define CAVS_VERSION_1_8 0x10800
|
||||
#define CAVS_VERSION_2_0 0x20000
|
||||
#define CAVS_VERSION_2_5 0x20500
|
||||
|
||||
/* CAVS version defined by CONFIG_CAVS_VER_*/
|
||||
#if CONFIG_SOC_SERIES_INTEL_CAVS_V15
|
||||
#define CAVS_VERSION CAVS_VERSION_1_5
|
||||
#elif CONFIG_SOC_SERIES_INTEL_CAVS_V18
|
||||
#define CAVS_VERSION CAVS_VERSION_1_8
|
||||
#elif CONFIG_SOC_SERIES_INTEL_CAVS_V20
|
||||
#define CAVS_VERSION CAVS_VERSION_2_0
|
||||
#elif CONFIG_SOC_SERIES_INTEL_CAVS_V25
|
||||
#define CAVS_VERSION CAVS_VERSION_2_5
|
||||
#endif
|
||||
|
||||
#endif /* __CAVS_VERSION_H__ */
|
||||
114
soc/xtensa/intel_adsp/common/include/ipc.h
Normal file
114
soc/xtensa/intel_adsp/common/include/ipc.h
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_PLATFORM_IPC_H__
|
||||
#define __INCLUDE_PLATFORM_IPC_H__
|
||||
|
||||
/** Shift-left bits to extract the global cmd type */
|
||||
#define ADSP_GLB_TYPE_SHIFT 28
|
||||
#define ADSP_GLB_TYPE_MASK (0xf << ADSP_GLB_TYPE_SHIFT)
|
||||
#define ADSP_GLB_TYPE(x) ((x) << ADSP_GLB_TYPE_SHIFT)
|
||||
|
||||
/** Shift-left bits to extract the command type */
|
||||
#define ADSP_CMD_TYPE_SHIFT 16
|
||||
#define ADSP_CMD_TYPE_MASK (0xfff << ADSP_CMD_TYPE_SHIFT)
|
||||
#define ADSP_CMD_TYPE(x) ((x) << ADSP_CMD_TYPE_SHIFT)
|
||||
|
||||
#define ADSP_IPC_FW_READY ADSP_GLB_TYPE(0x7U)
|
||||
|
||||
/* extended data types that can be appended onto end of adsp_ipc_fw_ready */
|
||||
enum adsp_ipc_ext_data {
|
||||
ADSP_IPC_EXT_DMA_BUFFER = 0,
|
||||
ADSP_IPC_EXT_WINDOW,
|
||||
};
|
||||
|
||||
enum adsp_ipc_region {
|
||||
ADSP_IPC_REGION_DOWNBOX = 0,
|
||||
ADSP_IPC_REGION_UPBOX,
|
||||
ADSP_IPC_REGION_TRACE,
|
||||
ADSP_IPC_REGION_DEBUG,
|
||||
ADSP_IPC_REGION_STREAM,
|
||||
ADSP_IPC_REGION_REGS,
|
||||
ADSP_IPC_REGION_EXCEPTION,
|
||||
};
|
||||
|
||||
/**
|
||||
* Structure Header - Header for all IPC structures except command structs.
|
||||
* The size can be greater than the structure size and that means there is
|
||||
* extended bespoke data beyond the end of the structure including variable
|
||||
* arrays.
|
||||
*/
|
||||
struct adsp_ipc_hdr {
|
||||
uint32_t size; /**< size of structure */
|
||||
} __packed;
|
||||
|
||||
/**
|
||||
* Command Header - Header for all IPC commands. Identifies IPC message.
|
||||
* The size can be greater than the structure size and that means there is
|
||||
* extended bespoke data beyond the end of the structure including variable
|
||||
* arrays.
|
||||
*/
|
||||
struct adsp_ipc_cmd_hdr {
|
||||
uint32_t size; /**< size of structure */
|
||||
uint32_t cmd; /**< command */
|
||||
} __packed;
|
||||
|
||||
/* FW version */
|
||||
struct adsp_ipc_fw_version {
|
||||
struct adsp_ipc_hdr hdr;
|
||||
uint16_t major;
|
||||
uint16_t minor;
|
||||
uint16_t micro;
|
||||
uint16_t build;
|
||||
uint8_t date[12];
|
||||
uint8_t time[10];
|
||||
uint8_t tag[6];
|
||||
uint32_t abi_version;
|
||||
|
||||
/* reserved for future use */
|
||||
uint32_t reserved[4];
|
||||
} __packed;
|
||||
|
||||
/* FW ready Message - sent by firmware when boot has completed */
|
||||
struct adsp_ipc_fw_ready {
|
||||
struct adsp_ipc_cmd_hdr hdr;
|
||||
uint32_t dspbox_offset; /* dsp initiated IPC mailbox */
|
||||
uint32_t hostbox_offset; /* host initiated IPC mailbox */
|
||||
uint32_t dspbox_size;
|
||||
uint32_t hostbox_size;
|
||||
struct adsp_ipc_fw_version version;
|
||||
|
||||
/* Miscellaneous flags */
|
||||
uint64_t flags;
|
||||
|
||||
/* reserved for future use */
|
||||
uint32_t reserved[4];
|
||||
} __packed;
|
||||
|
||||
struct adsp_ipc_ext_data_hdr {
|
||||
struct adsp_ipc_cmd_hdr hdr;
|
||||
uint32_t type; /* ADSP_IPC_EXT_ */
|
||||
} __packed;
|
||||
|
||||
struct adsp_ipc_window_elem {
|
||||
struct adsp_ipc_hdr hdr;
|
||||
uint32_t type; /* ADSP_IPC_REGION_ */
|
||||
uint32_t id; /* platform specific */
|
||||
uint32_t flags; /**< R, W, RW, etc */
|
||||
uint32_t size; /* size of region in bytes */
|
||||
|
||||
/* offset in window region as windows can be partitioned */
|
||||
uint32_t offset;
|
||||
} __packed;
|
||||
|
||||
/* extended data memory windows for IPC, trace and debug */
|
||||
struct adsp_ipc_window {
|
||||
struct adsp_ipc_ext_data_hdr ext_hdr;
|
||||
uint32_t num_windows;
|
||||
struct adsp_ipc_window_elem window[];
|
||||
} __packed;
|
||||
|
||||
#endif /* __INCLUDE_PLATFORM_IPC_H__ */
|
||||
164
soc/xtensa/intel_adsp/common/include/soc.h
Normal file
164
soc/xtensa/intel_adsp/common/include/soc.h
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
#include <adsp/cache.h>
|
||||
|
||||
#ifndef __INC_SOC_H
|
||||
#define __INC_SOC_H
|
||||
|
||||
/* macros related to interrupt handling */
|
||||
#define XTENSA_IRQ_NUM_SHIFT 0
|
||||
#define CAVS_IRQ_NUM_SHIFT 8
|
||||
#define XTENSA_IRQ_NUM_MASK 0xff
|
||||
#define CAVS_IRQ_NUM_MASK 0xff
|
||||
|
||||
/*
|
||||
* IRQs are mapped on 2 levels. 3rd and 4th level are left as 0x00.
|
||||
*
|
||||
* 1. Peripheral Register bit offset.
|
||||
* 2. CAVS logic bit offset.
|
||||
*/
|
||||
#define XTENSA_IRQ_NUMBER(_irq) \
|
||||
((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
|
||||
#define CAVS_IRQ_NUMBER(_irq) \
|
||||
(((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1)
|
||||
|
||||
/* Macro that aggregates the bi-level interrupt into an IRQ number */
|
||||
#define SOC_AGGREGATE_IRQ(cavs_irq, core_irq) \
|
||||
( \
|
||||
((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \
|
||||
(((cavs_irq + 1) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) \
|
||||
)
|
||||
|
||||
#define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc))
|
||||
#define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc))
|
||||
#define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc))
|
||||
#define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc))
|
||||
|
||||
#define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x)
|
||||
|
||||
#define IOAPIC_EDGE 0
|
||||
#define IOAPIC_HIGH 0
|
||||
|
||||
/* I2S */
|
||||
#define I2S_CAVS_IRQ(i2s_num) \
|
||||
SOC_AGGREGATE_IRQ(0, (i2s_num), CAVS_L2_AGG_INT_LEVEL5)
|
||||
|
||||
#define I2S0_CAVS_IRQ I2S_CAVS_IRQ(0)
|
||||
#define I2S1_CAVS_IRQ I2S_CAVS_IRQ(1)
|
||||
#define I2S2_CAVS_IRQ I2S_CAVS_IRQ(2)
|
||||
#define I2S3_CAVS_IRQ I2S_CAVS_IRQ(3)
|
||||
|
||||
#define SSP_MN_DIV_SIZE (8)
|
||||
#define SSP_MN_DIV_BASE(x) \
|
||||
(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
|
||||
|
||||
#define PDM_BASE 0x00010000
|
||||
|
||||
/* SOC DSP SHIM Registers */
|
||||
#define SOC_DSP_SHIM_REG_BASE 0x00001000
|
||||
|
||||
/* SOC DSP SHIM Register - Clock Control */
|
||||
#define SOC_CLKCTL_REQ_AUDIO_PLL_CLK BIT(31)
|
||||
#define SOC_CLKCTL_REQ_XTAL_CLK BIT(30)
|
||||
#define SOC_CLKCTL_REQ_FAST_CLK BIT(29)
|
||||
|
||||
#define SOC_CLKCTL_TCPLCG_POS(x) (16 + x)
|
||||
#define SOC_CLKCTL_TCPLCG_DIS(x) (1 << SOC_CLKCTL_TCPLCG_POS(x))
|
||||
|
||||
#define SOC_CLKCTL_DPCS_POS(x) (8 + x)
|
||||
#define SOC_CLKCTL_DPCS_DIV1(x) (0 << SOC_CLKCTL_DPCS_POS(x))
|
||||
#define SOC_CLKCTL_DPCS_DIV2(x) (1 << SOC_CLKCTL_DPCS_POS(x))
|
||||
#define SOC_CLKCTL_DPCS_DIV4(x) (3 << SOC_CLKCTL_DPCS_POS(x))
|
||||
|
||||
#define SOC_CLKCTL_TCPAPLLS BIT(7)
|
||||
|
||||
#define SOC_CLKCTL_LDCS_POS (5)
|
||||
#define SOC_CLKCTL_LDCS_LMPCS (0 << SOC_CLKCTL_LDCS_POS)
|
||||
#define SOC_CLKCTL_LDCS_LDOCS (1 << SOC_CLKCTL_LDCS_POS)
|
||||
|
||||
#define SOC_CLKCTL_HDCS_POS (4)
|
||||
#define SOC_CLKCTL_HDCS_HMPCS (0 << SOC_CLKCTL_HDCS_POS)
|
||||
#define SOC_CLKCTL_HDCS_HDOCS (1 << SOC_CLKCTL_HDCS_POS)
|
||||
|
||||
#define SOC_CLKCTL_LDOCS_POS (3)
|
||||
#define SOC_CLKCTL_LDOCS_PLL (0 << SOC_CLKCTL_LDOCS_POS)
|
||||
#define SOC_CLKCTL_LDOCS_FAST (1 << SOC_CLKCTL_LDOCS_POS)
|
||||
|
||||
#define SOC_CLKCTL_HDOCS_POS (2)
|
||||
#define SOC_CLKCTL_HDOCS_PLL (0 << SOC_CLKCTL_HDOCS_POS)
|
||||
#define SOC_CLKCTL_HDOCS_FAST (1 << SOC_CLKCTL_HDOCS_POS)
|
||||
|
||||
#define SOC_CLKCTL_LPMEM_PLL_CLK_SEL_POS (1)
|
||||
#define SOC_CLKCTL_LPMEM_PLL_CLK_SEL_DIV2 \
|
||||
(0 << SOC_CLKCTL_LPMEM_PLL_CLK_SEL_POS)
|
||||
#define SOC_CLKCTL_LPMEM_PLL_CLK_SEL_DIV4 \
|
||||
(1 << SOC_CLKCTL_LPMEM_PLL_CLK_SEL_POS)
|
||||
|
||||
#define SOC_CLKCTL_HPMEM_PLL_CLK_SEL_POS (0)
|
||||
#define SOC_CLKCTL_HPMEM_PLL_CLK_SEL_DIV2 \
|
||||
(0 << SOC_CLKCTL_HPMEM_PLL_CLK_SEL_POS)
|
||||
#define SOC_CLKCTL_HPMEM_PLL_CLK_SEL_DIV4 \
|
||||
(1 << SOC_CLKCTL_HPMEM_PLL_CLK_SEL_POS)
|
||||
|
||||
/* SOC DSP SHIM Register - Power Control */
|
||||
#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0 BIT(0)
|
||||
#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
|
||||
|
||||
/* DSP Wall Clock Timers (0 and 1) */
|
||||
#define DSP_WCT_IRQ(x) \
|
||||
SOC_AGGREGATE_IRQ((22 + x), CAVS_L2_AGG_INT_LEVEL2)
|
||||
|
||||
#define DSP_WCT_CS_TA(x) BIT(x)
|
||||
#define DSP_WCT_CS_TT(x) BIT(4 + x)
|
||||
|
||||
struct soc_dsp_shim_regs {
|
||||
uint32_t reserved[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t walclk32_lo;
|
||||
uint32_t walclk32_hi;
|
||||
};
|
||||
uint64_t walclk;
|
||||
};
|
||||
uint32_t dspwctcs;
|
||||
uint32_t reserved1[1];
|
||||
union {
|
||||
struct {
|
||||
uint32_t dspwct0c32_lo;
|
||||
uint32_t dspwct0c32_hi;
|
||||
};
|
||||
uint64_t dspwct0c;
|
||||
};
|
||||
union {
|
||||
struct {
|
||||
uint32_t dspwct1c32_lo;
|
||||
uint32_t dspwct1c32_hi;
|
||||
};
|
||||
uint64_t dspwct1c;
|
||||
};
|
||||
uint32_t reserved2[14];
|
||||
uint32_t clkctl;
|
||||
uint32_t clksts;
|
||||
uint32_t reserved3[4];
|
||||
uint16_t pwrctl;
|
||||
uint16_t pwrsts;
|
||||
uint32_t lpsctl;
|
||||
uint32_t lpsdmas0;
|
||||
uint32_t lpsdmas1;
|
||||
uint32_t reserved4[22];
|
||||
};
|
||||
|
||||
extern void z_soc_irq_enable(uint32_t irq);
|
||||
extern void z_soc_irq_disable(uint32_t irq);
|
||||
extern int z_soc_irq_is_enabled(unsigned int irq);
|
||||
|
||||
#endif /* __INC_SOC_H */
|
||||
34
soc/xtensa/intel_adsp/common/main_entry.S
Normal file
34
soc/xtensa/intel_adsp/common/main_entry.S
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright(c) 2017 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* Author: Rander Wang <rander.wang@intel.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Entry point from boot loader.
|
||||
* Fix link address of this entry to SOF_TEXT_START so that
|
||||
* it is easy for boot loader to jump to the baseFW because
|
||||
* the boot loader and baseFW are in different elf file.
|
||||
*/
|
||||
|
||||
|
||||
// Exports
|
||||
.global _MainEntry
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
|
||||
.begin literal_prefix .MainEntry
|
||||
.section .MainEntry.text, "ax"
|
||||
|
||||
.align 4
|
||||
.global _MainEntry
|
||||
|
||||
_MainEntry:
|
||||
|
||||
j __start
|
||||
|
||||
.size _MainEntry, . - _MainEntry
|
||||
|
||||
.end literal_prefix
|
||||
235
soc/xtensa/intel_adsp/common/soc.c
Normal file
235
soc/xtensa/intel_adsp/common/soc.c
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <device.h>
|
||||
#include <arch/xtensa/xtensa_api.h>
|
||||
#include <xtensa/xtruntime.h>
|
||||
#include <irq_nextlevel.h>
|
||||
#include <xtensa/hal.h>
|
||||
#include <init.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_INTERRUPTS
|
||||
#include <sw_isr_table.h>
|
||||
#endif
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
#include <logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
#define CAVS_INTC_NODE(n) DT_INST(n, intel_cavs_intc)
|
||||
|
||||
void z_soc_irq_enable(uint32_t irq)
|
||||
{
|
||||
const struct device *dev_cavs;
|
||||
|
||||
switch (XTENSA_IRQ_NUMBER(irq)) {
|
||||
case DT_IRQN(CAVS_INTC_NODE(0)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(1)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(2)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(3)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
|
||||
break;
|
||||
default:
|
||||
/* regular interrupt */
|
||||
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dev_cavs) {
|
||||
LOG_DBG("board: CAVS device binding failed");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The specified interrupt is in CAVS interrupt controller.
|
||||
* So enable core interrupt first.
|
||||
*/
|
||||
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
|
||||
|
||||
/* Then enable the interrupt in CAVS interrupt controller */
|
||||
irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
|
||||
}
|
||||
|
||||
void z_soc_irq_disable(uint32_t irq)
|
||||
{
|
||||
const struct device *dev_cavs;
|
||||
|
||||
switch (XTENSA_IRQ_NUMBER(irq)) {
|
||||
case DT_IRQN(CAVS_INTC_NODE(0)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(1)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(2)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(3)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
|
||||
break;
|
||||
default:
|
||||
/* regular interrupt */
|
||||
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dev_cavs) {
|
||||
LOG_DBG("board: CAVS device binding failed");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The specified interrupt is in CAVS interrupt controller.
|
||||
* So disable the interrupt in CAVS interrupt controller.
|
||||
*/
|
||||
irq_disable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
|
||||
|
||||
/* Then disable the parent IRQ if all children are disabled */
|
||||
if (!irq_is_enabled_next_level(dev_cavs)) {
|
||||
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
|
||||
}
|
||||
}
|
||||
|
||||
int z_soc_irq_is_enabled(unsigned int irq)
|
||||
{
|
||||
const struct device *dev_cavs;
|
||||
int ret = 0;
|
||||
|
||||
switch (XTENSA_IRQ_NUMBER(irq)) {
|
||||
case DT_IRQN(CAVS_INTC_NODE(0)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(0)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(1)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(1)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(2)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(2)));
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(3)):
|
||||
dev_cavs = device_get_binding(DT_LABEL(CAVS_INTC_NODE(3)));
|
||||
break;
|
||||
default:
|
||||
/* regular interrupt */
|
||||
ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!dev_cavs) {
|
||||
LOG_DBG("board: CAVS device binding failed");
|
||||
ret = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Then enable the interrupt in CAVS interrupt controller */
|
||||
ret = irq_line_is_enabled_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_INTERRUPTS
|
||||
int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
|
||||
void (*routine)(const void *parameter),
|
||||
const void *parameter, uint32_t flags)
|
||||
{
|
||||
uint32_t table_idx;
|
||||
uint32_t cavs_irq, cavs_idx;
|
||||
int ret;
|
||||
|
||||
ARG_UNUSED(flags);
|
||||
ARG_UNUSED(priority);
|
||||
|
||||
/* extract 2nd level interrupt number */
|
||||
cavs_irq = CAVS_IRQ_NUMBER(irq);
|
||||
ret = irq;
|
||||
|
||||
if (cavs_irq == 0) {
|
||||
/* Not affecting 2nd level interrupts */
|
||||
z_isr_install(irq, routine, parameter);
|
||||
goto irq_connect_out;
|
||||
}
|
||||
|
||||
/* Figure out the base index. */
|
||||
switch (XTENSA_IRQ_NUMBER(irq)) {
|
||||
case DT_IRQN(CAVS_INTC_NODE(0)):
|
||||
cavs_idx = 0;
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(1)):
|
||||
cavs_idx = 1;
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(2)):
|
||||
cavs_idx = 2;
|
||||
break;
|
||||
case DT_IRQN(CAVS_INTC_NODE(3)):
|
||||
cavs_idx = 3;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto irq_connect_out;
|
||||
}
|
||||
|
||||
table_idx = CONFIG_CAVS_ISR_TBL_OFFSET +
|
||||
CONFIG_MAX_IRQ_PER_AGGREGATOR * cavs_idx;
|
||||
table_idx += cavs_irq;
|
||||
|
||||
_sw_isr_table[table_idx].arg = parameter;
|
||||
_sw_isr_table[table_idx].isr = routine;
|
||||
|
||||
irq_connect_out:
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void soc_set_power_and_clock(void)
|
||||
{
|
||||
volatile struct soc_dsp_shim_regs *dsp_shim_regs =
|
||||
(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
|
||||
|
||||
/*
|
||||
* DSP Core 0 PLL Clock Select divide by 1
|
||||
* DSP Core 1 PLL Clock Select divide by 1
|
||||
* Low Power Domain Clock Select depends on LMPCS bit
|
||||
* High Power Domain Clock Select depands on HMPCS bit
|
||||
* Low Power Domain PLL Clock Select device by 4
|
||||
* High Power Domain PLL Clock Select device by 2
|
||||
* Tensilica Core Prevent Audio PLL Shutdown (TCPAPLLS)
|
||||
* Tensilica Core Prevent Local Clock Gating (Core 0)
|
||||
* Tensilica Core Prevent Local Clock Gating (Core 1)
|
||||
*/
|
||||
dsp_shim_regs->clkctl =
|
||||
SOC_CLKCTL_DPCS_DIV1(0) |
|
||||
SOC_CLKCTL_DPCS_DIV1(1) |
|
||||
SOC_CLKCTL_LDCS_LMPCS |
|
||||
SOC_CLKCTL_HDCS_HMPCS |
|
||||
SOC_CLKCTL_LPMEM_PLL_CLK_SEL_DIV4 |
|
||||
SOC_CLKCTL_HPMEM_PLL_CLK_SEL_DIV2 |
|
||||
SOC_CLKCTL_TCPAPLLS |
|
||||
SOC_CLKCTL_TCPLCG_DIS(0) |
|
||||
SOC_CLKCTL_TCPLCG_DIS(1);
|
||||
|
||||
/* Disable power gating for both cores */
|
||||
dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
|
||||
SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
|
||||
|
||||
/* Rewrite the low power sequencing control bits */
|
||||
dsp_shim_regs->lpsctl = dsp_shim_regs->lpsctl;
|
||||
}
|
||||
|
||||
static int soc_init(const struct device *dev)
|
||||
{
|
||||
soc_set_power_and_clock();
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(soc_init, PRE_KERNEL_1, 99);
|
||||
216
soc/xtensa/intel_adsp/common/soc_mp.c
Normal file
216
soc/xtensa/intel_adsp/common/soc_mp.c
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include <kernel.h>
|
||||
#include <kernel_structs.h>
|
||||
#include <toolchain.h>
|
||||
#include <sys/__assert.h>
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
|
||||
#include <logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#include <soc.h>
|
||||
#include <adsp/io.h>
|
||||
|
||||
#include <soc/shim.h>
|
||||
|
||||
#include <drivers/ipm.h>
|
||||
#include <ipm/ipm_cavs_idc.h>
|
||||
|
||||
#if CONFIG_MP_NUM_CPUS > 1 && !defined(CONFIG_IPM_CAVS_IDC)
|
||||
#error Need to enable the IPM driver for multiprocessing
|
||||
#endif
|
||||
|
||||
/* ROM wake version parsed by ROM during core wake up. */
|
||||
#define IDC_ROM_WAKE_VERSION 0x2
|
||||
|
||||
/* IDC message type. */
|
||||
#define IDC_TYPE_SHIFT 24
|
||||
#define IDC_TYPE_MASK 0x7f
|
||||
#define IDC_TYPE(x) (((x) & IDC_TYPE_MASK) << IDC_TYPE_SHIFT)
|
||||
|
||||
/* IDC message header. */
|
||||
#define IDC_HEADER_MASK 0xffffff
|
||||
#define IDC_HEADER(x) ((x) & IDC_HEADER_MASK)
|
||||
|
||||
/* IDC message extension. */
|
||||
#define IDC_EXTENSION_MASK 0x3fffffff
|
||||
#define IDC_EXTENSION(x) ((x) & IDC_EXTENSION_MASK)
|
||||
|
||||
/* IDC power up message. */
|
||||
#define IDC_MSG_POWER_UP \
|
||||
(IDC_TYPE(0x1) | IDC_HEADER(IDC_ROM_WAKE_VERSION))
|
||||
|
||||
#define IDC_MSG_POWER_UP_EXT(x) IDC_EXTENSION((x) >> 2)
|
||||
|
||||
static const struct device *idc;
|
||||
|
||||
extern void __start(void);
|
||||
|
||||
struct cpustart_rec {
|
||||
uint32_t cpu;
|
||||
|
||||
arch_cpustart_t fn;
|
||||
char *stack_top;
|
||||
void *arg;
|
||||
uint32_t vecbase;
|
||||
|
||||
uint32_t alive;
|
||||
|
||||
/* padding to cache line */
|
||||
uint8_t padding[XCHAL_DCACHE_LINESIZE - 6 * 4];
|
||||
};
|
||||
|
||||
static __aligned(XCHAL_DCACHE_LINESIZE)
|
||||
struct cpustart_rec start_rec;
|
||||
|
||||
static void *mp_top;
|
||||
|
||||
static void mp_entry2(void)
|
||||
{
|
||||
volatile int ie;
|
||||
uint32_t idc_reg;
|
||||
|
||||
/* Copy over VECBASE from the main CPU for an initial value
|
||||
* (will need to revisit this if we ever allow a user API to
|
||||
* change interrupt vectors at runtime).
|
||||
*/
|
||||
ie = 0;
|
||||
__asm__ volatile("wsr.INTENABLE %0" : : "r"(ie));
|
||||
__asm__ volatile("wsr.VECBASE %0" : : "r"(start_rec.vecbase));
|
||||
__asm__ volatile("rsync");
|
||||
|
||||
/* Set up the CPU pointer. */
|
||||
_cpu_t *cpu = &_kernel.cpus[start_rec.cpu];
|
||||
|
||||
__asm__ volatile(
|
||||
"wsr." CONFIG_XTENSA_KERNEL_CPU_PTR_SR " %0" : : "r"(cpu));
|
||||
|
||||
/* Clear busy bit set by power up message */
|
||||
idc_reg = idc_read(IPC_IDCTFC(0), start_rec.cpu) | IPC_IDCTFC_BUSY;
|
||||
idc_write(IPC_IDCTFC(0), start_rec.cpu, idc_reg);
|
||||
|
||||
#ifdef CONFIG_IPM_CAVS_IDC
|
||||
/* Interrupt must be enabled while running on current core */
|
||||
irq_enable(XTENSA_IRQ_NUMBER(DT_IRQN(DT_INST(0, intel_cavs_idc))));
|
||||
#endif /* CONFIG_IPM_CAVS_IDC */
|
||||
|
||||
start_rec.alive = 1;
|
||||
SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec));
|
||||
|
||||
start_rec.fn(start_rec.arg);
|
||||
|
||||
#if CONFIG_MP_NUM_CPUS == 1
|
||||
/* CPU#1 can be under manual control running custom functions
|
||||
* instead of participating in general thread execution.
|
||||
* Put the CPU into idle after those functions return
|
||||
* so this won't return.
|
||||
*/
|
||||
for (;;) {
|
||||
k_cpu_idle();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Defines a locally callable "function" named mp_stack_switch(). The
|
||||
* first argument (in register a2 post-ENTRY) is the new stack pointer
|
||||
* to go into register a1. The second (a3) is the entry point.
|
||||
* Because this never returns, a0 is used as a scratch register then
|
||||
* set to zero for the called function (a null return value is the
|
||||
* signal for "top of stack" to the debugger).
|
||||
*/
|
||||
void mp_stack_switch(void *stack, void *entry);
|
||||
__asm__("\n"
|
||||
".align 4 \n"
|
||||
"mp_stack_switch: \n\t"
|
||||
|
||||
"entry a1, 16 \n\t"
|
||||
|
||||
"movi a0, 0 \n\t"
|
||||
|
||||
"jx a3 \n\t");
|
||||
|
||||
/* Carefully constructed to use no stack beyond compiler-generated ABI
|
||||
* instructions. Stack pointer is pointing to __stack at this point.
|
||||
*/
|
||||
void z_mp_entry(void)
|
||||
{
|
||||
*(uint32_t *)CONFIG_SRAM_BASE_ADDRESS = 0xDEADBEEF;
|
||||
SOC_DCACHE_FLUSH((uint32_t *)CONFIG_SRAM_BASE_ADDRESS, 64);
|
||||
|
||||
mp_stack_switch(mp_top, mp_entry2);
|
||||
}
|
||||
|
||||
void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
|
||||
arch_cpustart_t fn, void *arg)
|
||||
{
|
||||
uint32_t vecbase;
|
||||
uint32_t idc_reg;
|
||||
|
||||
__ASSERT(cpu_num == 1, "Only supports only two CPUs!");
|
||||
|
||||
/* Setup data to boot core #1 */
|
||||
__asm__ volatile("rsr.VECBASE %0\n\t" : "=r"(vecbase));
|
||||
|
||||
start_rec.cpu = cpu_num;
|
||||
start_rec.fn = fn;
|
||||
start_rec.stack_top = Z_THREAD_STACK_BUFFER(stack) + sz;
|
||||
start_rec.arg = arg;
|
||||
start_rec.vecbase = vecbase;
|
||||
start_rec.alive = 0;
|
||||
|
||||
mp_top = Z_THREAD_STACK_BUFFER(stack) + sz;
|
||||
|
||||
SOC_DCACHE_FLUSH(&start_rec, sizeof(start_rec));
|
||||
|
||||
#ifdef CONFIG_IPM_CAVS_IDC
|
||||
idc = device_get_binding(DT_LABEL(DT_INST(0, intel_cavs_idc)));
|
||||
#endif
|
||||
|
||||
/* Enable IDC interrupt on the other core */
|
||||
idc_reg = idc_read(IPC_IDCCTL, cpu_num);
|
||||
idc_reg |= IPC_IDCCTL_IDCTBIE(0);
|
||||
idc_write(IPC_IDCCTL, cpu_num, idc_reg);
|
||||
sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
|
||||
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
|
||||
|
||||
/* Send power up message to the other core */
|
||||
idc_write(IPC_IDCIETC(cpu_num), 0, IDC_MSG_POWER_UP_EXT(RAM_BASE));
|
||||
idc_write(IPC_IDCITC(cpu_num), 0, IDC_MSG_POWER_UP | IPC_IDCITC_BUSY);
|
||||
|
||||
/* Disable IDC interrupt on other core so IPI won't cause
|
||||
* them to jump to ISR until the core is fully initialized.
|
||||
*/
|
||||
idc_reg = idc_read(IPC_IDCCTL, cpu_num);
|
||||
idc_reg &= ~IPC_IDCCTL_IDCTBIE(0);
|
||||
idc_write(IPC_IDCCTL, cpu_num, idc_reg);
|
||||
sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 +
|
||||
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
|
||||
|
||||
do {
|
||||
SOC_DCACHE_INVALIDATE(&start_rec, sizeof(start_rec));
|
||||
} while (start_rec.alive == 0);
|
||||
|
||||
/* Clear done bit from responding the power up message */
|
||||
idc_reg = idc_read(IPC_IDCIETC(cpu_num), 0) | IPC_IDCIETC_DONE;
|
||||
idc_write(IPC_IDCIETC(cpu_num), 0, idc_reg);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SCHED_IPI_SUPPORTED
|
||||
FUNC_ALIAS(soc_sched_ipi, arch_sched_ipi, void);
|
||||
void soc_sched_ipi(void)
|
||||
{
|
||||
if (idc != NULL) {
|
||||
ipm_send(idc, 0, IPM_CAVS_IDC_MSG_SCHED_IPI_ID,
|
||||
IPM_CAVS_IDC_MSG_SCHED_IPI_DATA, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue