diff --git a/boards/x86/arduino_101/dts.fixup b/boards/x86/arduino_101/dts.fixup index d446604356a..4f888f04e0b 100644 --- a/boards/x86/arduino_101/dts.fixup +++ b/boards/x86/arduino_101/dts.fixup @@ -7,3 +7,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/boards/x86/galileo/dts.fixup b/boards/x86/galileo/dts.fixup index e481ce5c544..9f80e096ff4 100644 --- a/boards/x86/galileo/dts.fixup +++ b/boards/x86/galileo/dts.fixup @@ -9,3 +9,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/boards/x86/minnowboard/dts.fixup b/boards/x86/minnowboard/dts.fixup index e481ce5c544..9f80e096ff4 100644 --- a/boards/x86/minnowboard/dts.fixup +++ b/boards/x86/minnowboard/dts.fixup @@ -9,3 +9,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/boards/x86/qemu_x86/dts.fixup b/boards/x86/qemu_x86/dts.fixup index e481ce5c544..9f80e096ff4 100644 --- a/boards/x86/qemu_x86/dts.fixup +++ b/boards/x86/qemu_x86/dts.fixup @@ -9,3 +9,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/boards/x86/quark_se_c1000_devboard/dts.fixup b/boards/x86/quark_se_c1000_devboard/dts.fixup index d446604356a..4f888f04e0b 100644 --- a/boards/x86/quark_se_c1000_devboard/dts.fixup +++ b/boards/x86/quark_se_c1000_devboard/dts.fixup @@ -7,3 +7,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/boards/x86/tinytile/dts.fixup b/boards/x86/tinytile/dts.fixup index d446604356a..4f888f04e0b 100644 --- a/boards/x86/tinytile/dts.fixup +++ b/boards/x86/tinytile/dts.fixup @@ -7,3 +7,5 @@ #define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS #define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS + +#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig index 5bded5e9cee..c9715a5e151 100644 --- a/drivers/interrupt_controller/Kconfig +++ b/drivers/interrupt_controller/Kconfig @@ -63,12 +63,14 @@ config IOAPIC_DEBUG help Enable debugging for IO-APIC driver. +if !HAS_DTS config IOAPIC_BASE_ADDRESS hex "IO-APIC Base Address" default 0xFEC00000 depends on IOAPIC help This option specifies the base address of the IO-APIC device. +endif config IOAPIC_NUM_RTES int "Number of Redirection Table Entries available" diff --git a/dts/arc/quark_se_c1000_ss.dtsi b/dts/arc/quark_se_c1000_ss.dtsi index dcfe13ad6ef..dc0fbf7e35f 100644 --- a/dts/arc/quark_se_c1000_ss.dtsi +++ b/dts/arc/quark_se_c1000_ss.dtsi @@ -45,7 +45,7 @@ uart0: uart@b0002000 { compatible = "intel,qmsi-uart"; reg = <0xb0002000 0x400>; - interrupts = <5 0>; + interrupts = <41 0>; interrupt-parent = <&core_intc>; label = "UART_0"; @@ -55,7 +55,7 @@ uart1: uart@b0002400 { compatible = "intel,qmsi-uart"; reg = <0xb0002400 0x400>; - interrupts = <6 0>; + interrupts = <42 0>; interrupt-parent = <&core_intc>; label = "UART_1"; diff --git a/dts/bindings/interrupt-controller/intel,ioapic.yaml b/dts/bindings/interrupt-controller/intel,ioapic.yaml new file mode 100644 index 00000000000..bf6e15c4a8a --- /dev/null +++ b/dts/bindings/interrupt-controller/intel,ioapic.yaml @@ -0,0 +1,33 @@ +--- +title: Intel I/O Advanced Programmable Interrupt Controller +version: 0.1 + +description: > + This binding describes the Intel I/O Advanced Programmable Interrupt + controller + +properties: + compatible: + category: required + type: string + description: compatible strings + constraint: "intel,ioapic" + + reg: + category: required + type: int + description: mmio register space + generation: define + + intel,num-irq-priority-bits: + category: required + type: int + description: number of bits of IRQ priorities + generation: define + +cell_string: IRQ + +"#cells": + - irq + - sense +... diff --git a/dts/bindings/interrupt-controller/intel,mvic.yaml b/dts/bindings/interrupt-controller/intel,mvic.yaml new file mode 100644 index 00000000000..568f7163a70 --- /dev/null +++ b/dts/bindings/interrupt-controller/intel,mvic.yaml @@ -0,0 +1,33 @@ +--- +title: Intel Quark D2000 Interrupt Controller +version: 0.1 + +description: > + This binding describes the Intel Quark D2000 Interrupt + Controller + +properties: + compatible: + category: required + type: string + description: compatible strings + constraint: "intel,mvic" + + reg: + category: required + type: int + description: mmio register space + generation: define + + intel,num-irq-priority-bits: + category: required + type: int + description: number of bits of IRQ priorities + generation: define + +cell_string: IRQ + +"#cells": + - irq + - sense +... diff --git a/dts/x86/atom.dtsi b/dts/x86/atom.dtsi index 26160d4053f..7112d2fd12e 100644 --- a/dts/x86/atom.dtsi +++ b/dts/x86/atom.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include #define __SIZE_K(x) (x * 1024) @@ -13,6 +14,12 @@ reg = <0>; }; + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + reg = <0xfec00000 0x100000>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; flash0: flash@00100000{ @@ -37,6 +44,8 @@ compatible = "ns16550"; reg = <0xf0008000 0x400>; label = "UART_0"; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; @@ -45,6 +54,8 @@ compatible = "ns16550"; reg = <0xf0009000 0x400>; label = "UART_1"; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; diff --git a/dts/x86/ia32.dtsi b/dts/x86/ia32.dtsi index f4d6419225e..f46763a1de9 100644 --- a/dts/x86/ia32.dtsi +++ b/dts/x86/ia32.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include #define __SIZE_K(x) (x * 1024) @@ -15,6 +16,14 @@ }; + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + reg = <0xfec00000 0x100000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + flash0: flash@00001000 { reg = <0x00001000 DT_FLASH_SIZE>; }; @@ -37,6 +46,8 @@ compatible = "ns16550"; reg = <0xf0008000 0x400>; label = "UART_0"; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; @@ -45,6 +56,8 @@ compatible = "ns16550"; reg = <0xf0009000 0x400>; label = "UART_1"; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; diff --git a/dts/x86/intel_curie.dtsi b/dts/x86/intel_curie.dtsi index 47a1ac29e94..a0802bea25b 100644 --- a/dts/x86/intel_curie.dtsi +++ b/dts/x86/intel_curie.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include #define __SIZE_K(x) (x * 1024) @@ -18,6 +19,13 @@ compatible = "arc"; reg = <1>; }; + + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + reg = <0xfec00000 0x100000>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; flash0: flash@40010000 { @@ -43,6 +51,9 @@ rtc: rtc@b0000400 { compatible = "intel,qmsi-rtc"; reg = <0xb0000400 0x400>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + clock-frequency = <32768>; }; @@ -50,6 +61,8 @@ compatible = "intel,qmsi-uart"; reg = <0xb0002000 0x400>; label = "UART_0"; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; status = "disabled"; }; @@ -58,6 +71,9 @@ compatible = "intel,qmsi-uart"; reg = <0xb0002400 0x400>; label = "UART_1"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + status = "disabled"; }; @@ -65,6 +81,8 @@ gpio: gpio@b000c000 { compatible = "intel,qmsi-gpio"; reg = <0xb00c00 0x400>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; diff --git a/dts/x86/intel_quark_d2000.dtsi b/dts/x86/intel_quark_d2000.dtsi index 9f0a2bf6282..2fb1e298db4 100644 --- a/dts/x86/intel_quark_d2000.dtsi +++ b/dts/x86/intel_quark_d2000.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include #define __SIZE_K(x) (x * 1024) @@ -13,6 +14,11 @@ reg = <0>; }; + intc: mvic@0 { + compatible = "intel,mvic"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; flash0: flash@00180000 { @@ -36,12 +42,17 @@ compatible = "intel,qmsi-rtc"; reg = <0xb0000400 0x400>; clock-frequency = <32768>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; + }; uart0: uart@b0002000 { compatible = "intel,qmsi-uart"; reg = <0xb0002000 0x400>; label = "UART_0"; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; status = "disabled"; }; @@ -50,6 +61,9 @@ compatible = "intel,qmsi-uart"; reg = <0xb0002400 0x400>; label = "UART_1"; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + status = "disabled"; }; @@ -57,6 +71,8 @@ gpio: gpio@b000c000 { compatible = "intel,qmsi-gpio"; reg = <0xb00c00 0x400>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; diff --git a/dts/x86/quark_x1000.dtsi b/dts/x86/quark_x1000.dtsi index 02f49faf394..0fdf9ce958a 100644 --- a/dts/x86/quark_x1000.dtsi +++ b/dts/x86/quark_x1000.dtsi @@ -1,4 +1,5 @@ #include "skeleton.dtsi" +#include #define __SIZE_K(x) (x * 1024) @@ -13,6 +14,12 @@ reg = <0>; }; + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + reg = <0xfec00000 0x100000>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; flash0: flash@00100000{ @@ -37,6 +44,8 @@ compatible = "ns16550"; reg = <0xf0008000 0x400>; label = "UART_0"; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; @@ -45,6 +54,8 @@ compatible = "ns16550"; reg = <0xf0009000 0x400>; label = "UART_1"; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&intc>; status = "disabled"; }; diff --git a/include/dt-bindings/interrupt-controller/intel-ioapic.h b/include/dt-bindings/interrupt-controller/intel-ioapic.h new file mode 100644 index 00000000000..1d4c65827d5 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/intel-ioapic.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __DT_BINDING_IRQ_H +#define __DT_BINDING_IRQ_H + +#define IRQ_TYPE_LEVEL 0x00008000 +#define IRQ_TYPE_EDGE 0x00000000 +#define IRQ_TYPE_LOW 0x00002000 +#define IRQ_TYPE_HIGH 0x00000000 +#define IRQ_TYPE_EDGE_RISING (IRQ_TYPE_EDGE | IRQ_TYPE_HIGH) +#define IRQ_TYPE_EDGE_FALLING (IRQ_TYPE_EDGE | IRQ_TYPE_LOW) +#define IRQ_TYPE_LEVEL_HIGH (IRQ_TYPE_LEVEL | IRQ_TYPE_HIGH) +#define IRQ_TYPE_LEVEL_LOW (IRQ_TYPE_LEVEL | IRQ_TYPE_LOW) + +#endif diff --git a/include/dt-bindings/interrupt-controller/intel-mvic.h b/include/dt-bindings/interrupt-controller/intel-mvic.h new file mode 100644 index 00000000000..f2ae68ebb7e --- /dev/null +++ b/include/dt-bindings/interrupt-controller/intel-mvic.h @@ -0,0 +1 @@ +#include "intel-ioapic.h"