SPARC: add FPU support
This change adds full shared floating point support for the SPARC architecture. All SPARC floating point registers are scratch registers with respect to function call boundaries. That means we only have to save floating point registers when switching threads in ISR. The registers are stored to the corresponding thread stack. FPU is disabled when calling ISR. Any attempt to use FPU in ISR will generate the fp_disabled trap which causes Zephyr fatal error. - This commit adds no new thread state. - All FPU contest save/restore is synchronous and lazy FPU context switch is not implemented. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
This commit is contained in:
Martin Åberg
Ioannis Glaropoulos
parent
356d37fb7f
commit
53a4acb2dc
5 changed files with 145 additions and 7 deletions
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@ -730,7 +730,7 @@ menu "Floating Point Options"
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config FPU
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bool "Enable floating point unit (FPU)"
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depends on CPU_HAS_FPU
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depends on ARC || ARM || RISCV || X86
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depends on ARC || ARM || RISCV || SPARC || X86
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help
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This option enables the hardware Floating Point Unit (FPU), in order to
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support using the floating point registers and instructions.
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@ -117,8 +117,30 @@ __sparc_trap_interrupt:
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*/
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/* Enable traps, raise PIL to mask all maskable interrupts. */
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or %l0, PSR_PIL, %o0
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wr %o0, PSR_ET, %psr
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or %l0, PSR_PIL, %l6
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#if defined(CONFIG_FPU)
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/*
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* We now check if the interrupted context was using the FPU. The
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* result is stored in register l5 which will either get the value 0
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* (FPU not used) or PSR_EF (FPU used).
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*
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* If the FPU was used by the interrupted context, then we do two
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* things:
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* 1. Store FSR to memory. This has the side-effect of completing all
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* pending FPU operations.
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* 2. Disable FPU. Floating point instructions in the ISR will trap.
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*
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* The FPU is be enabled again if needed after the ISR has returned.
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*/
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set PSR_EF, %l5
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andcc %l0, %l5, %l5
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bne,a 1f
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st %fsr, [%sp]
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1:
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andn %l6, %l5, %l6
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#endif
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wr %l6, PSR_ET, %psr
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nop
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nop
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nop
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@ -159,7 +181,69 @@ __sparc_trap_interrupt:
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*/
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cmp %o0, %o1
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beq .Lno_reschedule
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/* z_sparc_context_switch() is a leaf function not using stack. */
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add %sp, (96+8-64), %sp
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#if defined(CONFIG_FPU_SHARING)
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/* IF PSR_EF at trap time then store the FP context. */
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cmp %l5, 0
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be .Lno_fp_context
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nop
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/*
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* PSR_EF was 1 at trap time so save the FP registers on stack.
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* - Set PSR_EF so we can access the FP registers.
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* - Allocate space for the FP registers above the save area used for
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* the z_sparc_context_switch() call.
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*/
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wr %l6, %l5, %psr
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nop
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nop
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nop
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sub %sp, 34 * 4, %sp
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std %f0, [%sp + 64 + 0x00]
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std %f2, [%sp + 64 + 0x08]
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std %f4, [%sp + 64 + 0x10]
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std %f6, [%sp + 64 + 0x18]
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std %f8, [%sp + 64 + 0x20]
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std %f10, [%sp + 64 + 0x28]
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std %f12, [%sp + 64 + 0x30]
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std %f14, [%sp + 64 + 0x38]
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std %f16, [%sp + 64 + 0x40]
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std %f18, [%sp + 64 + 0x48]
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std %f20, [%sp + 64 + 0x50]
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std %f22, [%sp + 64 + 0x58]
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std %f24, [%sp + 64 + 0x60]
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std %f26, [%sp + 64 + 0x68]
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std %f28, [%sp + 64 + 0x70]
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std %f30, [%sp + 64 + 0x78]
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call z_sparc_context_switch
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st %fsr, [%sp + 64 + 0x80]
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ldd [%sp + 64 + 0x00], %f0
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ldd [%sp + 64 + 0x08], %f2
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ldd [%sp + 64 + 0x10], %f4
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ldd [%sp + 64 + 0x18], %f6
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ldd [%sp + 64 + 0x20], %f8
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ldd [%sp + 64 + 0x28], %f10
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ldd [%sp + 64 + 0x30], %f12
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ldd [%sp + 64 + 0x38], %f14
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ldd [%sp + 64 + 0x40], %f16
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ldd [%sp + 64 + 0x48], %f18
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ldd [%sp + 64 + 0x50], %f20
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ldd [%sp + 64 + 0x58], %f22
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ldd [%sp + 64 + 0x60], %f24
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ldd [%sp + 64 + 0x68], %f26
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ldd [%sp + 64 + 0x70], %f28
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ldd [%sp + 64 + 0x78], %f30
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ld [%sp + 64 + 0x80], %fsr
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ba .Lno_reschedule
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add %sp, 34 * 4, %sp
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.Lno_fp_context:
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#endif /* CONFIG_FPU_SHARING */
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call z_sparc_context_switch
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nop
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.Lno_reschedule:
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@ -27,6 +27,12 @@ struct init_stack_frame {
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uint32_t pad[8];
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};
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#if defined(CONFIG_FPU_SHARING)
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#define USER_FP_MASK K_FP_REGS
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#else
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#define USER_FP_MASK 0
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#endif
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void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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char *stack_ptr, k_thread_entry_t entry,
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void *p1, void *p2, void *p3)
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@ -47,6 +53,16 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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thread->callee_saved.o7 = (uint32_t) z_thread_entry_wrapper - 8;
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thread->callee_saved.psr = PSR_S | PSR_PS | PSR_ET;
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if (IS_ENABLED(CONFIG_FPU_SHARING)) {
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/* Selected threads can use the FPU */
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if (thread->base.user_options & USER_FP_MASK) {
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thread->callee_saved.psr |= PSR_EF;
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}
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} else if (IS_ENABLED(CONFIG_FPU)) {
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/* Any thread can use the FPU */
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thread->callee_saved.psr |= PSR_EF;
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}
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thread->switch_handle = thread;
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}
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@ -56,3 +72,10 @@ void *z_arch_get_next_switch_handle(struct k_thread **old_thread)
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return z_get_next_switch_handle(*old_thread);
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}
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#if defined(CONFIG_FPU_SHARING)
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int arch_float_disable(struct k_thread *thread)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_FPU_SHARING */
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@ -1,7 +1,9 @@
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# SPDX-License-Identifier: Apache-2.0
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list(APPEND TOOLCHAIN_C_FLAGS -msoft-float)
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list(APPEND TOOLCHAIN_LD_FLAGS -msoft-float)
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if(NOT CONFIG_FPU)
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list(APPEND TOOLCHAIN_C_FLAGS -msoft-float)
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list(APPEND TOOLCHAIN_LD_FLAGS -msoft-float)
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endif()
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if(CONFIG_SPARC_CASA)
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# SPARC V8, mul/div, casa
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@ -9,8 +9,9 @@ configurations that support these registers.
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.. note::
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Floating point services are currently available only for boards
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based on ARM Cortex-M SoCs supporting the Floating Point Extension,
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the Intel x86 architecture and ARCv2 SoCs supporting the Floating
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Point Extension. The services provided are architecture specific.
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the Intel x86 architecture, the SPARC architecture and ARCv2 SoCs
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supporting the Floating Point Extension. The services provided
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are architecture specific.
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The kernel does not support the use of floating point registers by ISRs.
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@ -176,6 +177,34 @@ FP context of threads that are not using the FP registers. An extra 84 bytes
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(single floating point hardware) or 164 bytes (double floating point hardware)
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of stack space is required to load and store floating point registers.
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SPARC architecture
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------------------
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On the SPARC architecture, the kernel treats each thread as a non-user
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or FPU user and the thread must be tagged by one of the
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following techniques:
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* A statically-created thread can be tagged by passing the
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:c:macro:`K_FP_REGS` option to :c:macro:`K_THREAD_DEFINE`.
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* A dynamically-created thread can be tagged by passing the
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:c:macro:`K_FP_REGS` to :c:func:`k_thread_create`.
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During thread context switch at exit from interrupt handler, the SPARC
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kernel saves *all* floating point registers, if the FPU was enabled in
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the switched-out thread. Floating point registers are saved on the thread's
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stack. Floating point registers are restored when a thread context is restored
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iff they were saved at the context save. Saving and restoring of the floating
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point registers is synchronous and thus not lazy. The FPU is always disabled
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when an ISR is called (independent of :option:`CONFIG_FPU_SHARING`).
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Floating point disabling with :c:func:`k_float_disable` is not implemented.
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When :option:`CONFIG_FPU_SHARING` is used, then 136 bytes of stack space
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is required for each FPU user thread to load and store floating point
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registers. No extra stack is required if :option:`CONFIG_FPU_SHARING` is
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not used.
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x86 architecture
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----------------
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