From 537798db0d82c1b6c6f2d6fb029210ef007ebf6e Mon Sep 17 00:00:00 2001 From: Diego Sueiro Date: Wed, 17 Oct 2018 07:58:14 +0100 Subject: [PATCH] soc: arm: exx32: Add Silabs EFR32MG12P soc files The Silicon Labs EFR32MG12P Mighty Gecko MCU includes: * Cortex-M4F core at 40MHz * up to 1024KB of flash and 256KB of RAM * integrated Sub-GHz and/or 2.4GHz radio * multiple low power peripherals Signed-off-by: Diego Sueiro Signed-off-by: Endre Karlson --- dts/arm/silabs/efr32mg.dtsi | 157 ++++++++++++++++++ dts/arm/silabs/efr32mg12p332f1024gl125.dtsi | 18 ++ .../gpio/silabs,efr32mg12-gpio-port.yaml | 31 ++++ dts/bindings/gpio/silabs,efr32mg12-gpio.yaml | 34 ++++ dts/bindings/i2c/silabs,gecko-i2c.yaml | 40 +++++ dts/bindings/serial/silabs,gecko-leuart.yaml | 35 ++++ ext/hal/silabs/gecko/CMakeLists.txt | 15 +- soc/arm/silabs_exx32/Kconfig | 8 +- .../efr32mg12p/Kconfig.defconfig.efr32mg12p | 42 +++++ .../efr32mg12p/Kconfig.defconfig.series | 21 +++ .../silabs_exx32/efr32mg12p/Kconfig.series | 16 ++ soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc | 33 ++++ soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 88 ++++++++++ soc/arm/silabs_exx32/efr32mg12p/linker.ld | 16 ++ soc/arm/silabs_exx32/efr32mg12p/soc.h | 36 ++++ soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h | 63 +++++++ 16 files changed, 645 insertions(+), 8 deletions(-) create mode 100644 dts/arm/silabs/efr32mg.dtsi create mode 100644 dts/arm/silabs/efr32mg12p332f1024gl125.dtsi create mode 100644 dts/bindings/gpio/silabs,efr32mg12-gpio-port.yaml create mode 100644 dts/bindings/gpio/silabs,efr32mg12-gpio.yaml create mode 100644 dts/bindings/i2c/silabs,gecko-i2c.yaml create mode 100644 dts/bindings/serial/silabs,gecko-leuart.yaml create mode 100644 soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p create mode 100644 soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series create mode 100644 soc/arm/silabs_exx32/efr32mg12p/Kconfig.series create mode 100644 soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc create mode 100644 soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h create mode 100644 soc/arm/silabs_exx32/efr32mg12p/linker.ld create mode 100644 soc/arm/silabs_exx32/efr32mg12p/soc.h create mode 100644 soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi new file mode 100644 index 00000000000..f45c8b56856 --- /dev/null +++ b/dts/arm/silabs/efr32mg.dtsi @@ -0,0 +1,157 @@ +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + usart0: usart@40010000 { /* USART0 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010000 0x400>; + interrupts = <12 0>, <13 0>; + interrupt-names = "rx", "tx"; + status = "disabled"; + label = "USART_0"; + }; + + usart1: usart@40010400 { /* USART1 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010400 0x400>; + interrupts = <20 0>, <21 0>; + interrupt-names = "rx", "tx"; + status = "disabled"; + label = "USART_1"; + }; + + usart2: usart@40010800 { /* USART2 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010800 0x400>; + interrupts = <40 0>, <41 0>; + interrupt-names = "rx", "tx"; + status = "disabled"; + label = "USART_2"; + }; + + usart3: usart@40010C00 { /* USART3 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010C00 0x400>; + interrupts = <43 0>, <44 0>; + interrupt-names = "rx", "tx"; + status = "disabled"; + label = "USART_3"; + }; + + leuart0: leuart@4004A000 { /* LEUART0 */ + compatible = "silabs,gecko-leuart"; + reg = <0x4004A000 0x400>; + interrupts = <22 0>; + status = "disabled"; + label = "LEUART_0"; + }; + + i2c0: i2c@4000C000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000C000 0x400>; + interrupts = <17 0>; + label = "I2C_0"; + status = "disabled"; + }; + + i2c1: i2c@4000C400 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4000C400 0x400>; + interrupts = <42 0>; + label = "I2C_1"; + status = "disabled"; + }; + + gpio@4000a400 { + compatible = "silabs,efr32mg-gpio"; + reg = <0x4000a400 0xc00>; + interrupts = <9 2 17 2>; + interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + label = "GPIO"; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@4000a000 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a000 0x30>; + label = "GPIO_A"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiob: gpio@4000a030 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a030 0x30>; + label = "GPIO_B"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioc: gpio@4000a060 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a060 0x30>; + label = "GPIO_C"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiod: gpio@4000a090 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a090 0x30>; + label = "GPIO_D"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioe: gpio@4000a0c0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000a0c0 0x30>; + label = "GPIO_E"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiof: gpio@4000a0f0 { + compatible = "silabs,efr32mg-gpio-port"; + reg = <0x4000af0 0x30>; + label = "GPIO_F"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi b/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi new file mode 100644 index 00000000000..a9502070145 --- /dev/null +++ b/dts/arm/silabs/efr32mg12p332f1024gl125.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash@0 { + reg = <0 DT_SIZE_K(1024)>; + }; + + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(256)>; + }; +}; diff --git a/dts/bindings/gpio/silabs,efr32mg12-gpio-port.yaml b/dts/bindings/gpio/silabs,efr32mg12-gpio-port.yaml new file mode 100644 index 00000000000..db115c887b5 --- /dev/null +++ b/dts/bindings/gpio/silabs,efr32mg12-gpio-port.yaml @@ -0,0 +1,31 @@ +--- +title: EFR32MG GPIO +version: 0.1 + +description: > + This is a representation of the EFR32MG GPIO Port nodes + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "silabs,efr32mg-gpio-port" + generation: define + + reg: + type: int + description: mmio register space + generation: define + category: required + + label: + type: string + category: required + description: Human readable string describing the device (used by Zephyr for API name) + generation: define + +"#cells": + - pin + - flags +... diff --git a/dts/bindings/gpio/silabs,efr32mg12-gpio.yaml b/dts/bindings/gpio/silabs,efr32mg12-gpio.yaml new file mode 100644 index 00000000000..feef52d069a --- /dev/null +++ b/dts/bindings/gpio/silabs,efr32mg12-gpio.yaml @@ -0,0 +1,34 @@ +--- +title: EFR32MG GPIO +version: 0.1 + +description: > + This is a representation of the EFR32MG GPIO nodes + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "silabs,efr32mg-gpio" + generation: define + + reg: + type: int + description: mmio register space + generation: define + category: required + + interrupts: + type: compound + category: required + description: required interrupts + generation: define + + label: + type: string + category: required + description: Human readable string describing the device (used by Zephyr for API name) + generation: define + +... diff --git a/dts/bindings/i2c/silabs,gecko-i2c.yaml b/dts/bindings/i2c/silabs,gecko-i2c.yaml new file mode 100644 index 00000000000..48a2e69e75e --- /dev/null +++ b/dts/bindings/i2c/silabs,gecko-i2c.yaml @@ -0,0 +1,40 @@ +# +# Copyright (c) 2018 Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# +--- +title: Silabs Gecko I2C Controller +version: 0.1 + +description: > + This is a representation of the Silabs Gecko I2C nodes + +inherits: + !include i2c.yaml + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "silabs,gecko-i2c" + + reg: + type: int + description: mmio register space + generation: define + category: required + + interrupts: + type: compound + category: required + description: required interrupts + generation: define + + location: + type: int + category: required + description: PIN location + generation: define +... diff --git a/dts/bindings/serial/silabs,gecko-leuart.yaml b/dts/bindings/serial/silabs,gecko-leuart.yaml new file mode 100644 index 00000000000..953bbb9a669 --- /dev/null +++ b/dts/bindings/serial/silabs,gecko-leuart.yaml @@ -0,0 +1,35 @@ +--- +title: GECKO LEUART +version: 0.1 + +description: > + This binding gives a base representation of the Gecko LEUART + +inherits: + !include uart.yaml + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "silabs,gecko-leuart" + + reg: + type: array + description: mmio register space + generation: define + category: required + + interrupts: + type: array + category: required + description: required interrupts + generation: define + + location: + type: int + category: required + description: PIN location + generation: define +... diff --git a/ext/hal/silabs/gecko/CMakeLists.txt b/ext/hal/silabs/gecko/CMakeLists.txt index 3b74e015467..e1d91e44c33 100644 --- a/ext/hal/silabs/gecko/CMakeLists.txt +++ b/ext/hal/silabs/gecko/CMakeLists.txt @@ -22,11 +22,12 @@ zephyr_compile_definitions( ${SILABS_GECKO_PART_NUMBER} ) -zephyr_sources( emlib/src/em_system.c) -zephyr_sources_ifdef(CONFIG_HAS_CMU emlib/src/em_cmu.c) -zephyr_sources_ifdef(CONFIG_GPIO_GECKO emlib/src/em_gpio.c) -zephyr_sources_ifdef(CONFIG_UART_GECKO emlib/src/em_usart.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG Device/SiliconLabs/EFM32WG/Source/system_efm32wg.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P Device/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32HG Device/SiliconLabs/EFM32HG/Source/system_efm32hg.c) +zephyr_sources( emlib/src/em_system.c) +zephyr_sources_ifdef(CONFIG_HAS_CMU emlib/src/em_cmu.c) +zephyr_sources_ifdef(CONFIG_HAS_EMU emlib/src/em_emu.c) +zephyr_sources_ifdef(CONFIG_GPIO_GECKO emlib/src/em_gpio.c) +zephyr_sources_ifdef(CONFIG_UART_GECKO emlib/src/em_usart.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG Device/SiliconLabs/EFM32WG/Source/system_efm32wg.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P Device/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32HG Device/SiliconLabs/EFM32HG/Source/system_efm32hg.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32MG12P Device/SiliconLabs/EFR32MG12P/Source/system_efr32mg12p.c) diff --git a/soc/arm/silabs_exx32/Kconfig b/soc/arm/silabs_exx32/Kconfig index fc4a4c1cdc2..3a179430f91 100644 --- a/soc/arm/silabs_exx32/Kconfig +++ b/soc/arm/silabs_exx32/Kconfig @@ -17,14 +17,20 @@ source "soc/arm/silabs_exx32/*/Kconfig.soc" config SOC_PART_NUMBER string - default SOC_PART_NUMBER_EXX32_EFM32WG if SOC_SERIES_EFM32WG + default SOC_PART_NUMBER_EXX32_EFM32WG if SOC_SERIES_EFM32WG default SOC_PART_NUMBER_EXX32_EFR32FG1P if SOC_SERIES_EFR32FG1P default SOC_PART_NUMBER_EXX32_EFM32HG if SOC_SERIES_EFM32HG + default SOC_PART_NUMBER_EXX32_EFR32MG12P if SOC_SERIES_EFR32MG12P help This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. +config HAS_EMU + bool + help + Set if the energy management unit (EMU) is present in the SoC. + config HAS_CMU bool help diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p new file mode 100644 index 00000000000..fd9fc363e6d --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.efr32mg12p @@ -0,0 +1,42 @@ +# Kconfig - Silicon Labs EFR32MG12P platform configuration options + +# +# Copyright (c) 2018 Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_EFR32MG12P + +config SOC + string + default "efr32mg12p" + +config GPIO + def_bool y + +if GPIO + +config GPIO_GECKO + def_bool y + +endif # GPIO + +if SERIAL + +config UART_GECKO + def_bool y + +config LEUART_GECKO + def_bool y + +endif # SERIAL + +if I2C + +config I2C_GECKO + def_bool y + +endif # I2C + +endif # SOC_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series new file mode 100644 index 00000000000..5c4f2bfb4ca --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series @@ -0,0 +1,21 @@ +# Kconfig - EFM32WG series configuration options + +# +# Copyright (c) 2018 Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_EFR32MG12P + +config SOC_SERIES + default "efr32mg12p" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 49 + +gsource "soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.e*" + +endif # SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series new file mode 100644 index 00000000000..7a6f9f79189 --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series @@ -0,0 +1,16 @@ +# Kconfig - EFR32MG12P MCU line +# +# Copyright (c) 2018 Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_EFR32MG12P + bool "EFR32MG12P Series MCU" + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select SOC_FAMILY_EXX32 + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_SYSTICK + help + Enable support for EFR32 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc new file mode 100644 index 00000000000..731092b163b --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc @@ -0,0 +1,33 @@ +# Kconfig - EFR32MG12P MCU line +# +# Copyright (c) 2018 Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "EFR32 Mighty Gecko MCU Selection" +depends on SOC_SERIES_EFR32MG12P + +config SOC_EFR32MG12P + bool "SOC_EFR32MG12P" + select HAS_SILABS_GECKO + select HAS_CMU + select HAS_EMU + +endchoice + +if SOC_SERIES_EFR32MG12P + +config SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + bool + +config SOC_PART_NUMBER_EXX32_EFR32MG12P + string + default "EFR32MG12P332F1024GL125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +endif # SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h new file mode 100644 index 00000000000..fadfc113c88 --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -0,0 +1,88 @@ +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + +/* SoC level DTS fixup file */ + +#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +#define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_40010000_BASE_ADDRESS +#define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_40010000_CURRENT_SPEED +#define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_40010000_IRQ_0 +#define CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY SILABS_GECKO_USART_40010000_IRQ_0_PRIORITY +#define CONFIG_USART_GECKO_0_IRQ_TX SILABS_GECKO_USART_40010000_IRQ_1 +#define CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY SILABS_GECKO_USART_40010000_IRQ_1_PRIORITY +#define CONFIG_USART_GECKO_0_LABEL SILABS_GECKO_USART_40010000_LABEL +#define CONFIG_USART_GECKO_0_LOCATION SILABS_GECKO_USART_40010000_LOCATION +#define CONFIG_USART_GECKO_0_SIZE SILABS_GECKO_USART_40010000_SIZE + +#define CONFIG_USART_GECKO_1_BASE_ADDRESS SILABS_GECKO_USART_40010400_BASE_ADDRESS +#define CONFIG_USART_GECKO_1_CURRENT_SPEED SILABS_GECKO_USART_40010400_CURRENT_SPEED +#define CONFIG_USART_GECKO_1_IRQ_RX SILABS_GECKO_USART_40010400_IRQ_0 +#define CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY SILABS_GECKO_USART_40010400_IRQ_0_PRIORITY +#define CONFIG_USART_GECKO_1_IRQ_TX SILABS_GECKO_USART_40010400_IRQ_1 +#define CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY SILABS_GECKO_USART_40010400_IRQ_1_PRIORITY +#define CONFIG_USART_GECKO_1_LABEL SILABS_GECKO_USART_40010400_LABEL +#define CONFIG_USART_GECKO_1_LOCATION SILABS_GECKO_USART_40010400_LOCATION +#define CONFIG_USART_GECKO_1_SIZE SILABS_GECKO_USART_40010400_SIZE + +#define CONFIG_USART_GECKO_2_BASE_ADDRESS SILABS_GECKO_USART_40010800_BASE_ADDRESS +#define CONFIG_USART_GECKO_2_CURRENT_SPEED SILABS_GECKO_USART_40010800_CURRENT_SPEED +#define CONFIG_USART_GECKO_2_IRQ_RX SILABS_GECKO_USART_40010800_IRQ_0 +#define CONFIG_USART_GECKO_2_IRQ_RX_PRIORITY SILABS_GECKO_USART_40010800_IRQ_0_PRIORITY +#define CONFIG_USART_GECKO_2_IRQ_TX SILABS_GECKO_USART_40010800_IRQ_1 +#define CONFIG_USART_GECKO_2_IRQ_TX_PRIORITY SILABS_GECKO_USART_40010800_IRQ_1_PRIORITY +#define CONFIG_USART_GECKO_2_LABEL SILABS_GECKO_USART_40010800_LABEL +#define CONFIG_USART_GECKO_2_LOCATION SILABS_GECKO_USART_40010800_LOCATION +#define CONFIG_USART_GECKO_2_SIZE SILABS_GECKO_USART_40010800_SIZE + +#define CONFIG_USART_GECKO_3_BASE_ADDRESS SILABS_GECKO_USART_40010C00_BASE_ADDRESS +#define CONFIG_USART_GECKO_3_CURRENT_SPEED SILABS_GECKO_USART_40010C00_CURRENT_SPEED +#define CONFIG_USART_GECKO_3_IRQ_RX SILABS_GECKO_USART_40010C00_IRQ_0 +#define CONFIG_USART_GECKO_3_IRQ_RX_PRIORITY SILABS_GECKO_USART_40010C00_IRQ_0_PRIORITY +#define CONFIG_USART_GECKO_3_IRQ_TX SILABS_GECKO_USART_40010C00_IRQ_1 +#define CONFIG_USART_GECKO_3_IRQ_TX_PRIORITY SILABS_GECKO_USART_40010C00_IRQ_1_PRIORITY +#define CONFIG_USART_GECKO_3_LABEL SILABS_GECKO_USART_40010C00_LABEL +#define CONFIG_USART_GECKO_3_LOCATION SILABS_GECKO_USART_40010C00_LOCATION +#define CONFIG_USART_GECKO_3_SIZE SILABS_GECKO_USART_40010C00_SIZE + +#define CONFIG_LEUART_GECKO_0_BASE_ADDRESS SILABS_GECKO_LEUART_4004A000_BASE_ADDRESS +#define CONFIG_LEUART_GECKO_0_CURRENT_SPEED SILABS_GECKO_LEUART_4004A000_CURRENT_SPEED +#define CONFIG_LEUART_GECKO_0_IRQ SILABS_GECKO_LEUART_4004A000_IRQ_0 +#define CONFIG_LEUART_GECKO_0_IRQ_PRIORITY SILABS_GECKO_LEUART_4004A000_IRQ_0_PRIORITY +#define CONFIG_LEUART_GECKO_0_LABEL SILABS_GECKO_LEUART_4004A000_LABEL +#define CONFIG_LEUART_GECKO_0_LOCATION SILABS_GECKO_LEUART_4004A000_LOCATION +#define CONFIG_LEUART_GECKO_0_SIZE SILABS_GECKO_LEUART_4004A000_SIZE + +#define CONFIG_GPIO_GECKO_COMMON_NAME SILABS_EFR32MG_GPIO_4000A400_LABEL +#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN +#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY +#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD +#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY + +#define CONFIG_GPIO_GECKO_PORTA_NAME SILABS_EFR32MG_GPIO_PORT_4000A000_LABEL +#define CONFIG_GPIO_GECKO_PORTB_NAME SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL +#define CONFIG_GPIO_GECKO_PORTC_NAME SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL +#define CONFIG_GPIO_GECKO_PORTD_NAME SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL +#define CONFIG_GPIO_GECKO_PORTE_NAME SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL +#define CONFIG_GPIO_GECKO_PORTF_NAME SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL + +#define CONFIG_I2C_GECKO_0_BASE_ADDRESS SILABS_GECKO_I2C_4000C000_BASE_ADDRESS +#define CONFIG_I2C_GECKO_0_CLOCK_FREQUENCY SILABS_GECKO_I2C_4000C000_CLOCK_FREQUENCY +#define CONFIG_I2C_GECKO_0_IRQ SILABS_GECKO_I2C_4000C000_IRQ_0 +#define CONFIG_I2C_GECKO_0_IRQ_PRIORITY SILABS_GECKO_I2C_4000C000_IRQ_0_PRIORITY +#define CONFIG_I2C_GECKO_0_LABEL SILABS_GECKO_I2C_4000C000_LABEL +#define CONFIG_I2C_GECKO_0_LOCATION SILABS_GECKO_I2C_4000C000_LOCATION +#define CONFIG_I2C_GECKO_0_SIZE SILABS_GECKO_I2C_4000C000_SIZE + +#define CONFIG_I2C_GECKO_1_BASE_ADDRESS SILABS_GECKO_I2C_4000C400_BASE_ADDRESS +#define CONFIG_I2C_GECKO_1_CLOCK_FREQUENCY SILABS_GECKO_I2C_4000C400_CLOCK_FREQUENCY +#define CONFIG_I2C_GECKO_1_IRQ SILABS_GECKO_I2C_4000C400_IRQ_0 +#define CONFIG_I2C_GECKO_1_IRQ_PRIORITY SILABS_GECKO_I2C_4000C400_IRQ_0_PRIORITY +#define CONFIG_I2C_GECKO_1_LABEL SILABS_GECKO_I2C_4000C400_LABEL +#define CONFIG_I2C_GECKO_1_LOCATION SILABS_GECKO_I2C_4000C400_LOCATION +#define CONFIG_I2C_GECKO_1_SIZE SILABS_GECKO_I2C_4000C400_SIZE + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efr32mg12p/linker.ld b/soc/arm/silabs_exx32/efr32mg12p/linker.ld new file mode 100644 index 00000000000..47dafd0af97 --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/linker.ld @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Diego Sueiro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * This is the linker script for both standard images. + */ + +#include + +#include diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc.h b/soc/arm/silabs_exx32/efr32mg12p/soc.h new file mode 100644 index 00000000000..18aec1420e3 --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/soc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 Christian Taedcke, Diego Sueiro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the efm32wg soc + * + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _ASMLANGUAGE + +#include +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + +#endif /* !_ASMLANGUAGE */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC__H_ */ diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h new file mode 100644 index 00000000000..255f12dbace --- /dev/null +++ b/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018 Christian Taedcke, Diego Sueiro + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFR32MG MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SOC_PINMAP_H_ +#define _SOC_PINMAP_H_ + +#include + +#ifdef CONFIG_UART_GECKO +#ifdef CONFIG_USART_GECKO_0 +#if (CONFIG_USART_GECKO_0_LOCATION == 0) +#define PIN_USART0_TXD {gpioPortA, 0, gpioModePushPull, 1} +#define PIN_USART0_RXD {gpioPortA, 1, gpioModeInput, 0} +#else +#error ("Serial Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_USART_GECKO_0 */ +#endif /* CONFIG_UART_GECKO */ + +#ifdef CONFIG_LEUART_GECKO +#ifdef CONFIG_LEUART_GECKO_0 +#if (CONFIG_LEUART_GECKO_0_LOCATION == 27) +#define PIN_LEUART0_TXD {gpioPortF, 3, gpioModePushPull, 1} +#define PIN_LEUART0_RXD {gpioPortF, 4, gpioModeInput, 1} +#else +#error ("Serial Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_LEUART_GECKO_0 */ +#endif /* CONFIG_LEUART_GECKO */ + +#ifdef CONFIG_I2C_GECKO +#ifdef CONFIG_I2C_0 +#if (CONFIG_I2C_GECKO_0_LOCATION == 15) +#define PIN_I2C0_SDA {gpioPortC, 10, gpioModeWiredAnd, 1} +#define PIN_I2C0_SCL {gpioPortC, 11, gpioModeWiredAnd, 1} +#else +#error ("I2C Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_I2C_0 */ + +#ifdef CONFIG_I2C_1 +#if (CONFIG_I2C_GECKO_1_LOCATION == 17) +#define PIN_I2C1_SDA {gpioPortC, 4, gpioModeWiredAnd, 1} +#define PIN_I2C1_SCL {gpioPortC, 5, gpioModeWiredAnd, 1} +#else +#error ("I2C Driver for Gecko MCUs not implemented for this location index") +#endif +#endif /* CONFIG_I2C_1 */ +#endif /* CONFIG_I2C_GECKO */ + +#else +#error ("Pinmap not available for this Mighty Gecko MCU") + +#endif /* _SOC_PINMAP_H_ */