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tests/drivers/clock_control: stm32_common: Test HCLCK instead of SYSCLK

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Rework test_*_freq to test HCLK freq instead of SYSCLK one, as it is not
correct to compare CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC with SYSCLK.

Additionally, add a test to verify use of AHB prescaler.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-04-06 13:55:58 +02:00 • committed by Carles Cufí
commit 531c484958
3 changed files with 48 additions and 7 deletions
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30
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/f2_f4_f7_pll_100_hsi_16_ahb_2.overlay Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <200>;
div-p = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(50)>; /* Pll Output (100) / AHB prescaler */
apb1-prescaler = <2>;
apb2-prescaler = <2>;
};

22
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/src/test_stm32_clock_configuration.c
View file

@ -8,19 +8,27 @@
#include <soc.h>
#include <drivers/clock_control.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <stm32_ll_rcc.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(test);
#if defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX)
#define CALC_HCLK_FREQ __LL_RCC_CALC_HCLK1_FREQ
#else
#define CALC_HCLK_FREQ __LL_RCC_CALC_HCLK_FREQ
#endif
static void test_sysclk_freq(void)
static void test_hclk_freq(void)
{
uint32_t soc_sys_clk_freq;
uint32_t soc_hclk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
soc_hclk_freq = CALC_HCLK_FREQ(HAL_RCC_GetSysClockFreq(),
LL_RCC_GetAHBPrescaler());
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq,
"Expected hclck_freq: %d. Actual hclck_freq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq);
}
static void test_sysclk_src(void)
@ -102,7 +110,7 @@ void test_main(void)
{
printk("testing clock config on %s\n", CONFIG_BOARD);
ztest_test_suite(test_stm32_syclck_config,
ztest_unit_test(test_sysclk_freq),
ztest_unit_test(test_hclk_freq),
ztest_unit_test(test_sysclk_src),
ztest_unit_test(test_pll_src)
);

3
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
View file

@ -115,3 +115,6 @@ tests:
drivers.stm32_clock_configuration.common.f2_f4_f7.sysclksrc_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_64_hse_8.overlay"
platform_allow: nucleo_f207zg nucleo_f429zi nucleo_f446re nucleo_f746zg
drivers.stm32_clock_configuration.common.f2_f4_f7.sysclksrc_pll_100_hsi_16_ahb2:
extra_args: DTC_OVERLAY_FILE="boards/clear_f2_f4_f7_clocks.overlay;boards/f2_f4_f7_pll_100_hsi_16_ahb_2.overlay"
platform_allow: nucleo_f207zg nucleo_f429zi nucleo_f446re nucleo_f746zg