board: imx8mn_evk: enable ENET ethernet on Cortex-A Core
Enabled ENET ethernet port on Cortex-A Core for imx8mn EVK board. Updated document for supported features. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
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8 changed files with 175 additions and 2 deletions
44
boards/nxp/imx8mn_evk/Kconfig.defconfig
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44
boards/nxp/imx8mn_evk/Kconfig.defconfig
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@ -0,0 +1,44 @@
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_IMX8MN_EVK
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if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
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if NETWORKING
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config NET_L2_ETHERNET
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default y
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config NET_TX_STACK_SIZE
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default 8192
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config NET_RX_STACK_SIZE
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default 8192
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if NET_TCP
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config NET_TCP_WORKQ_STACK_SIZE
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default 8192
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endif # NET_TCP
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if NET_MGMT_EVENT
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config NET_MGMT_EVENT_STACK_SIZE
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default 8192
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endif # NET_MGMT_EVENT
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if NET_SOCKETS_SERVICE
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config NET_SOCKETS_SERVICE_STACK_SIZE
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default 8192
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endif # NET_SOCKETS_SERVICE
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endif # NETWORKING
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endif # BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
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endif # BOARD_IMX8MN_EVK
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@ -55,8 +55,18 @@ features:
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+-----------+------------+-------------------------------------+
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| ARM TIMER | on-chip | system clock |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| RDC | on-chip | Resource Domain Controller |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+-----------+------------+-------------------------------------+
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| GPT | on-chip | timer |
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+-----------+------------+-------------------------------------+
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| ENET | on-chip | ethernet port |
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+-----------+------------+-------------------------------------+
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Devices
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========
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@ -25,4 +25,42 @@
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};
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};
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pinmux_enet: pinmux_enet {
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group0 {
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pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
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<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
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<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
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<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
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<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
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<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
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slew-rate = "fast";
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drive-strength = "x6";
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};
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group1 {
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pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
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<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
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<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
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<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
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<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
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<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
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slew-rate = "fast";
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drive-strength = "x1";
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};
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group2 {
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pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
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slew-rate = "fast";
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drive-strength = "x1";
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};
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};
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pinmux_mdio: pinmux_mdio {
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group0 {
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pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
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<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
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slew-rate = "slow";
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drive-strength = "x6";
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};
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};
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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};
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};
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&enet {
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status = "okay";
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};
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&enet_mac {
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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phy-handle = <&phy>;
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zephyr,random-mac-address;
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phy-connection-type = "rgmii";
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status = "okay";
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};
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&enet_mdio {
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pinctrl-0 = <&pinmux_mdio>;
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pinctrl-names = "default";
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status = "okay";
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phy: phy@0 {
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compatible = "qca,ar8031";
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reg = <0>;
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status = "okay";
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};
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};
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&uart4 {
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current-speed = <115200>;
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pinctrl-0 = <&uart4_default>;
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@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# Serial Drivers
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CONFIG_SERIAL=y
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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};
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};
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&enet {
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status = "okay";
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};
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&enet_mac {
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pinctrl-0 = <&pinmux_enet>;
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pinctrl-names = "default";
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phy-handle = <&phy>;
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zephyr,random-mac-address;
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phy-connection-type = "rgmii";
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status = "okay";
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};
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&enet_mdio {
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pinctrl-0 = <&pinmux_mdio>;
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pinctrl-names = "default";
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status = "okay";
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phy: phy@0 {
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compatible = "qca,ar8031";
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reg = <0>;
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status = "okay";
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};
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};
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&uart4 {
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current-speed = <115200>;
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pinctrl-0 = <&uart4_default>;
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@ -13,6 +13,7 @@ CONFIG_ICACHE_LINE_SIZE_DETECT=y
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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CONFIG_KERNEL_DIRECT_MAP=y
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# SMP
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CONFIG_SMP=y
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