arm: cmsis: Convert _Scb*Fault*Reset to use direct CMSIS register access

Coverted:
	_ScbMemFaultMmfarReset
	_ScbBusFaultBfarReset
	_ScbUsageFaultAllFaultsReset

To use direct CMSIS register access.

Also removed scb.h and references as there is no longer any code in it.

Jira: ZEP-1568

Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

arch/arm/core/fault.c

@@ -76,18 +76,20 @@ void _FaultDump(const NANO_ESF *esf, int fault)
 	if (SCB->CFSR & CFSR_MMARVALID_Msk) {
 		PR_EXC("MMFAR: 0x%" PRIx32 "\n", SCB->MMFAR);
 		if (escalation) {
-			_ScbMemFaultMmfarReset();
+			/* clear MMAR[VALID] to reset */
+			SCB->CFSR &= ~CFSR_MMARVALID_Msk;
 		}
 	}
 	if (SCB->CFSR & CFSR_BFARVALID_Msk) {
 		PR_EXC("BFAR: 0x%" PRIx32 "\n", SCB->BFAR);
 		if (escalation) {
-			_ScbBusFaultBfarReset();
+			/* clear CFSR_BFAR[VALID] to reset */
+			SCB->CFSR &= ~CFSR_BFARVALID_Msk;
 		}
 	}
 
 	/* clear USFR sticky bits */
-	_ScbUsageFaultAllFaultsReset();
+	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M */
@@ -136,7 +138,8 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
 		if (SCB->CFSR & CFSR_MMARVALID_Msk) {
 			PR_EXC("  Address: 0x%" PRIx32 "\n", SCB->MMFAR);
 			if (fromHardFault) {
-				_ScbMemFaultMmfarReset();
+				/* clear MMAR[VALID] to reset */
+				SCB->CFSR &= ~CFSR_MMARVALID_Msk;
 			}
 		}
 	} else if (SCB->CFSR & CFSR_IACCVIOL_Msk) {
@@ -167,7 +170,8 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
 		if (SCB->CFSR & CFSR_BFARVALID_Msk) {
 			PR_EXC("  Address: 0x%" PRIx32 "\n", SCB->BFAR);
 			if (fromHardFault) {
-				_ScbBusFaultBfarReset();
+				/* clear CFSR_BFAR[VALID] to reset */
+				SCB->CFSR &= ~CFSR_BFARVALID_Msk;
 			}
 		}
 		/* it's possible to have both a precise and imprecise fault */
@@ -215,7 +219,8 @@ static void _UsageFault(const NANO_ESF *esf)
 		PR_EXC("  Attempt to execute undefined instruction\n");
 	}
 
-	_ScbUsageFaultAllFaultsReset();
+	/* clear USFR sticky bits */
+	SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
 }
 
 /**

include/arch/arm/arch.h

@@ -34,7 +34,6 @@ extern "C" {
 #include <arch/arm/cortex_m/error.h>
 #include <arch/arm/cortex_m/misc.h>
 #include <arch/arm/cortex_m/scs.h>
-#include <arch/arm/cortex_m/scb.h>
 #include <arch/arm/cortex_m/memory_map.h>
 #include <arch/arm/cortex_m/asm_inline.h>
 #include <arch/arm/cortex_m/addr_types.h>

include/arch/arm/cortex_m/scb.h

@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2013-2014 Wind River Systems, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief ARM CORTEX-M System Control Block interface
- *
- * Provide an interface to the System Control Block found on ARM Cortex-M
- * processors.
- *
- * The API does not account for all possible usages of the SCB, only the
- * functionalities needed by the kernel. It does not contain NVIC
- * functionalities either: these can be found in nvic.h. MPU functionalities
- * are not implemented.
- *
- * The same effect can be achieved by directly writing in the registers of the
- * SCB, with the layout available from scs.h, using the __scs.scb data
- * structure (or hardcoded values), but the APIs found here are less
- * error-prone, especially for registers with multiple instances to account
- * for 16 exceptions.
- *
- * If access to a missing functionality is needed, directly writing to the
- * registers is the way to implement it.
- */
-
-#ifndef _SCB__H_
-#define _SCB__H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef _ASMLANGUAGE
-
-#else
-
-#include <kernel.h>
-#include <arch/cpu.h>
-#include <misc/__assert.h>
-#include <arch/arm/cortex_m/scs.h>
-#include <misc/util.h>
-#include <stdint.h>
-
-#if defined(CONFIG_ARMV6_M)
-#elif defined(CONFIG_ARMV7_M)
-/**
- *
- * @brief Invalid the value in MMFAR
- *
- * This routine invalidates the MMFAR value. This should be done after
- * processing an MPU fault.
- *
- * @return N/A
- */
-
-static inline void _ScbMemFaultMmfarReset(void)
-{
-	__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid = 0;
-}
-
-/**
- *
- * @brief Invalid the value in BFAR
- *
- * This routine clears/invalidates the Bus Fault Address Register.
- * It should be done after processing a bus fault.
- *
- * @return N/A
- */
-
-static inline void _ScbBusFaultBfarReset(void)
-{
-	__scs.scb.cfsr.byte.bfsr.bit.bfarvalid = 0;
-}
-
-/**
- *
- * @brief Clear all usage faults (UFSR register)
- *
- * CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
- *
- * @return N/A
- */
-
-static inline void _ScbUsageFaultAllFaultsReset(void)
-{
-	__scs.scb.cfsr.byte.ufsr.val = 0xffff;
-}
-
-#else
-#error Unknown ARM architecture
-#endif /* CONFIG_ARMV6_M */
-
-#endif /* _ASMLANGUAGE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SCB__H_ */