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arm: cmsis: Convert _Scb*Fault*Reset to use direct CMSIS register access

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Coverted:
	_ScbMemFaultMmfarReset
	_ScbBusFaultBfarReset
	_ScbUsageFaultAllFaultsReset

To use direct CMSIS register access.

Also removed scb.h and references as there is no longer any code in it.

Jira: ZEP-1568

Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-27 20:39:33 -06:00 • committed by Maureen Helm
commit 52cf45c62a
3 changed files with 11 additions and 110 deletions
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1
include/arch/arm/arch.h
View file

@ -34,7 +34,6 @@ extern "C" {
#include <arch/arm/cortex_m/error.h>
#include <arch/arm/cortex_m/misc.h>
#include <arch/arm/cortex_m/scs.h>
#include <arch/arm/cortex_m/scb.h>
#include <arch/arm/cortex_m/memory_map.h>
#include <arch/arm/cortex_m/asm_inline.h>
#include <arch/arm/cortex_m/addr_types.h>

103
include/arch/arm/cortex_m/scb.h
View file

@ -1,103 +0,0 @@
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM CORTEX-M System Control Block interface
*
* Provide an interface to the System Control Block found on ARM Cortex-M
* processors.
*
* The API does not account for all possible usages of the SCB, only the
* functionalities needed by the kernel. It does not contain NVIC
* functionalities either: these can be found in nvic.h. MPU functionalities
* are not implemented.
*
* The same effect can be achieved by directly writing in the registers of the
* SCB, with the layout available from scs.h, using the __scs.scb data
* structure (or hardcoded values), but the APIs found here are less
* error-prone, especially for registers with multiple instances to account
* for 16 exceptions.
*
* If access to a missing functionality is needed, directly writing to the
* registers is the way to implement it.
*/
#ifndef _SCB__H_
#define _SCB__H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _ASMLANGUAGE
#else
#include <kernel.h>
#include <arch/cpu.h>
#include <misc/__assert.h>
#include <arch/arm/cortex_m/scs.h>
#include <misc/util.h>
#include <stdint.h>
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Invalid the value in MMFAR
*
* This routine invalidates the MMFAR value. This should be done after
* processing an MPU fault.
*
* @return N/A
*/
static inline void _ScbMemFaultMmfarReset(void)
{
__scs.scb.cfsr.byte.mmfsr.bit.mmarvalid = 0;
}
/**
*
* @brief Invalid the value in BFAR
*
* This routine clears/invalidates the Bus Fault Address Register.
* It should be done after processing a bus fault.
*
* @return N/A
*/
static inline void _ScbBusFaultBfarReset(void)
{
__scs.scb.cfsr.byte.bfsr.bit.bfarvalid = 0;
}
/**
*
* @brief Clear all usage faults (UFSR register)
*
* CFSR/UFSR register is a 'write-one-to-clear' (W1C) register.
*
* @return N/A
*/
static inline void _ScbUsageFaultAllFaultsReset(void)
{
__scs.scb.cfsr.byte.ufsr.val = 0xffff;
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
#endif /* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _SCB__H_ */