drivers: ipm: Add support for NXP i.MX rev2 MU
With a number of the i.MX SoCs (e.g., the i.MX8M Plus), NXP has moved to supporting the integrated Cortex-M cores with the MCUXpresso SDK (MCUX). As a result, certain Zephyr drivers (such as the IPM driver) need to be updated to utlize this new MCUX-based SDK. This change adds support for the MCUX Messaging Unit driver pulled in by this PR: https://github.com/zephyrproject-rtos/hal_nxp/pull/130 Additionally, this change enables the new IPM_IMX_REV2 config for the mimx8ml8_m7 SoC target which utilizes this new revision of the driver. Signed-off-by: Chris Trowbridge <chris.trowbridge@lairdconnect.com>
This commit is contained in:
Chris Trowbridge
David Leach
parent
9df8151623
commit
52bee41bba
4 changed files with 144 additions and 6 deletions
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@ -11,7 +11,11 @@
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#include <device.h>
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#include <soc.h>
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#include <drivers/ipm.h>
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#if IS_ENABLED(CONFIG_IPM_IMX_REV2)
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#include "fsl_mu.h"
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#else
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#include <mu_imx.h>
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#endif
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#define MU(config) ((MU_Type *)config->base)
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@ -31,6 +35,64 @@ struct imx_mu_data {
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void *user_data;
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};
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#if IS_ENABLED(CONFIG_IPM_IMX_REV2)
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/*!
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* @brief Check RX full status.
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*
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* This function checks the specific receive register full status.
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*
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* @param base Register base address for the module.
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* @param index RX register index to check.
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* @retval true RX register is full.
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* @retval false RX register is not full.
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*/
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static inline bool MU_IsRxFull(MU_Type *base, uint32_t index)
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{
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switch (index) {
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case 0:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx0FullFlag);
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case 1:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx1FullFlag);
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case 2:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx2FullFlag);
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case 3:
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return (bool)(MU_GetStatusFlags(base) & kMU_Rx3FullFlag);
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default:
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/* This shouldn't happen */
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assert(false);
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return false;
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}
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}
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/*!
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* @brief Check TX empty status.
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*
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* This function checks the specific transmit register empty status.
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*
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* @param base Register base address for the module.
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* @param index TX register index to check.
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* @retval true TX register is empty.
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* @retval false TX register is not empty.
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*/
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static inline bool MU_IsTxEmpty(MU_Type *base, uint32_t index)
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{
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switch (index) {
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case 0:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx0EmptyFlag);
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case 1:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx1EmptyFlag);
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case 2:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx2EmptyFlag);
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case 3:
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return (bool)(MU_GetStatusFlags(base) & kMU_Tx3EmptyFlag);
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default:
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/* This shouldn't happen */
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assert(false);
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return false;
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}
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}
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#endif
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static void imx_mu_isr(const struct device *dev)
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{
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const struct imx_mu_config *config = dev->config;
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@ -62,9 +124,14 @@ static void imx_mu_isr(const struct device *dev)
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}
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if (all_registers_full) {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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#if IS_ENABLED(CONFIG_IPM_IMX_REV2)
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data32[i] = MU_ReceiveMsg(base,
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(id * IMX_IPM_DATA_REGS) + i);
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#else
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MU_ReceiveMsg(base,
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(id * IMX_IPM_DATA_REGS) + i,
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&data32[i]);
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#endif
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}
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if (data->callback) {
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@ -79,9 +146,13 @@ static void imx_mu_isr(const struct device *dev)
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
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* Store immediate overlapping exception return operation
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* might vector to incorrect interrupt
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* might vector to incorrect interrupt. For Cortex-M7, if
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* core speed much faster than peripheral register write
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* speed, the peripheral interrupt flags may be still set
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* after exiting ISR, this results to the same error similar
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* with errata 838869.
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*/
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
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__DSB();
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#endif
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}
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@ -92,7 +163,9 @@ static int imx_mu_ipm_send(const struct device *dev, int wait, uint32_t id,
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const struct imx_mu_config *config = dev->config;
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MU_Type *base = MU(config);
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uint32_t data32[IMX_IPM_DATA_REGS];
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#if !IS_ENABLED(CONFIG_IPM_IMX_REV2)
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mu_status_t status;
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#endif
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int i;
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if (id > CONFIG_IPM_IMX_MAX_ID_VAL) {
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@ -106,6 +179,27 @@ static int imx_mu_ipm_send(const struct device *dev, int wait, uint32_t id,
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/* Actual message is passing using 32 bits registers */
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memcpy(data32, data, size);
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#if IS_ENABLED(CONFIG_IPM_IMX_REV2)
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if (wait) {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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MU_SendMsgNonBlocking(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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}
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while (!MU_IsTxEmpty(base,
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(id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
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}
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} else {
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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if (MU_IsTxEmpty(base, id * IMX_IPM_DATA_REGS + i)) {
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MU_SendMsg(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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} else {
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return -EBUSY;
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}
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}
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}
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#else
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for (i = 0; i < IMX_IPM_DATA_REGS; i++) {
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status = MU_TrySendMsg(base, id * IMX_IPM_DATA_REGS + i,
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data32[i]);
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@ -119,6 +213,7 @@ static int imx_mu_ipm_send(const struct device *dev, int wait, uint32_t id,
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(id * IMX_IPM_DATA_REGS) + IMX_IPM_DATA_REGS - 1)) {
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}
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}
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#endif
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return 0;
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}
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@ -151,7 +246,37 @@ static int imx_mu_ipm_set_enabled(const struct device *dev, int enable)
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{
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const struct imx_mu_config *config = dev->config;
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MU_Type *base = MU(config);
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#if IS_ENABLED(CONFIG_IPM_IMX_REV2)
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#if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx0FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx2FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx0FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx2FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_8
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx1FullInterruptEnable);
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#elif CONFIG_IPM_IMX_MAX_DATA_SIZE_16
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if (enable) {
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MU_EnableInterrupts(base, kMU_Rx3FullInterruptEnable);
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} else {
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MU_DisableInterrupts(base, kMU_Rx3FullInterruptEnable);
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}
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#else
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#error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
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#endif
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#else
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#if CONFIG_IPM_IMX_MAX_DATA_SIZE_4
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if (enable) {
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MU_EnableRxFullInt(base, 0U);
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@ -180,6 +305,7 @@ static int imx_mu_ipm_set_enabled(const struct device *dev, int enable)
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}
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#else
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#error "CONFIG_IPM_IMX_MAX_DATA_SIZE_n is not set"
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#endif
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#endif
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return 0;
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