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dts: arm: Add base DTS support for STM32 Nucleo board

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This patch adds the base DTS and yaml files required to support DTS
for the STM32L476 based Nucleo board.

Change-Id: Ic606a895a25f27d2990f651d0f3c3c5d84818cfd
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-02-04 23:29:41 -06:00 • committed by Anas Nashif
commit 52bca037be
5 changed files with 280 additions and 0 deletions
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158
dts/arm/stm32l476.dtsi Normal file
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/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "armv7-m.dtsi"
/ {
sram0: memory {
reg = <0x20000000 0x18000>;
};
flash0: flash {
reg = <0x08000000 0x100000>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37>;
zephyr,irq-prio = <0>;
baud-rate = <115200>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
zephyr,irq-prio = <0>;
baud-rate = <115200>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
zephyr,irq-prio = <0>;
baud-rate = <115200>;
status = "disabled";
};
uart4: uart@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
zephyr,irq-prio = <0>;
baud-rate = <115200>;
status = "disabled";
};
uart5: uart@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
zephyr,irq-prio = <0>;
baud-rate = <115200>;
status = "disabled";
};
syscfg: system-config@40010000 {
compatible = "syscon";
reg = <0x40013800 0x400>;
};
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32l4xx-pinctrl";
ranges = <0 0x48000000 0x2000>;
pins-are-numbered;
gpioa: gpio@48000000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
st,bank-name = "GPIOA";
};
gpiob: gpio@48000400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
st,bank-name = "GPIOB";
};
gpioc: gpio@48000800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
st,bank-name = "GPIOC";
};
gpiod: gpio@48000c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
st,bank-name = "GPIOD";
};
gpioe: gpio@48001000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
st,bank-name = "GPIOE";
};
gpiof: gpio@48001400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
st,bank-name = "GPIOF";
};
gpiog: gpio@48001800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
st,bank-name = "GPIOG";
};
gpioh: gpio@48001c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
st,bank-name = "GPIOH";
};
};
};
};
&nvic {
num-irq-prio-bits = <4>;
num-irqs = <82>;
};