dts: boards: arm: Rework FlexSPI bindings on i.MX RT boards

Reworks the NXP FlexSPI device tree bindings to configure controller and
device properties needed for an upcoming FlexSPI flash driver.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts

@@ -46,7 +46,7 @@ arduino_serial: &lpuart1 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(16)>;
 	at25sf128a: at25sf128a@0 {
-		compatible = "adesto,at25sf128a", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <134217728>;
 		label = "AT25SF128A";
 		reg = <0>;

boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts

@@ -75,7 +75,7 @@ arduino_serial: &lpuart4 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(16)>;
 	at25sf128a: at25sf128a@0 {
-		compatible = "adesto,at25sf128a", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <134217728>;
 		label = "AT25SF128A";
 		reg = <0>;

boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts

@@ -82,7 +82,7 @@ arduino_serial: &lpuart2 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
-		compatible = "issi,is25wp064", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <67108864>;
 		label = "IS25WP064";
 		reg = <0>;

boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts

@@ -93,7 +93,7 @@ arduino_serial: &lpuart3 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
 	s26ks512s0: s26ks512s@0 {
-		compatible = "cypress,s26ks512s";
+		compatible = "nxp,imx-flexspi-hyperflash";
 		size = <DT_SIZE_M(64*8)>;
 		label = "S26KS512S";
 		reg = <0>;

boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts

@@ -11,7 +11,7 @@
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
-		compatible = "issi,is25wp064", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <67108864>;
 		label = "IS25WP064";
 		reg = <0>;

boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts

@@ -94,7 +94,7 @@ arduino_serial: &lpuart3 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
-		compatible = "issi,is25wp064", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <67108864>;
 		label = "IS25WP064";
 		reg = <0>;

boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts

@@ -10,7 +10,7 @@
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
 	s26ks512s0: s26ks512s@0 {
-		compatible = "cypress,s26ks512s";
+		compatible = "nxp,imx-flexspi-hyperflash";
 		size = <DT_SIZE_M(64*8)>;
 		label = "S26KS512S";
 		reg = <0>;

boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts

@@ -135,7 +135,7 @@ arduino_i2c: &lpi2c1 {};
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
-		compatible = "issi,is25wp064", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <67108864>;
 		label = "IS25WP064";
 		reg = <0>;

boards/arm/mm_swiftio/mm_swiftio.dts

@@ -55,7 +55,7 @@
 &flexspi {
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
-		compatible = "issi,is25wp064", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <67108864>;
 		label = "IS25WP064";
 		reg = <0>;

dts/arm/nxp/nxp_rt.dtsi

@@ -72,6 +72,9 @@
 			label = "FLEXSPI";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			ahb-bufferable;
+			ahb-cacheable;
+			status = "disabled";
 		};
 
 		flexspi2: spi@402a4000 {
@@ -81,6 +84,9 @@
 			label = "FLEXSPI1";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			ahb-bufferable;
+			ahb-cacheable;
+			status = "disabled";
 		};
 
 		semc: semc0@402f0000 {

dts/arm/nxp/nxp_rt1064.dtsi

@@ -10,7 +10,7 @@
 	reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(4)>;
 	/* WINBOND */
 	w25q32jvwj0: w25q32jvwj@0 {
-		compatible = "winbond,w25q32jvwj", "jedec,spi-nor";
+		compatible = "nxp,imx-flexspi-nor";
 		size = <33554432>;
 		label = "W25Q32JVWJ0";
 		reg = <0>;

dts/bindings/mtd/nxp,imx-flexspi-device.yaml

@@ -0,0 +1,101 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI device
+
+compatible: "nxp,imx-flexspi-device"
+
+include: [spi-device.yaml, "jedec,jesd216.yaml"]
+
+properties:
+    cs-interval-unit:
+      type: int
+      required: false
+      default: 1
+      enum:
+        - 1
+        - 256
+      description: |
+        Chip select interval units, in serial clock cycles. See the
+        CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Minimum interval between chip select deassertion and assertion. See the
+        CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
+        default corresponds to the reset value of the register field.
+
+    cs-setup-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select setup time, in serial clock cycles. See the TCSS field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    cs-hold-time:
+      type: int
+      required: false
+      default: 3
+      description: |
+        Chip select hold time, in serial clock cycles. See the TCSH field in
+        registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
+        reset value of the register field.
+
+    data-valid-time:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Data valid time, in nanoseconds. See the registers DLLACR through
+        DLLBCR.
+
+    column-space:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Column address bit width. Set to zero if the flash does not support
+        column address. See the CAS field in registers FLASHA1CR0 through
+        FLASHB2CR0. The default corresponds to the reset value of the register
+        field.
+
+    word-addressable:
+      type: boolean
+      required: false
+      description: |
+        Don't transmit the least significant address bit when the flash is word
+        addressable. See the WA field in registers FLASHA1CR0 through
+        FLASHB2CR0.
+
+    ahb-write-wait-unit:
+      type: int
+      required: false
+      default: 2
+      enum:
+        - 2
+        - 8
+        - 32
+        - 128
+        - 512
+        - 2048
+        - 8192
+        - 32768
+      description: |
+        AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.
+
+    ahb-write-wait-interval:
+      type: int
+      required: false
+      default: 0
+      description: |
+        Time to wait between AHB triggered command sequences. See the AWRWAIT
+        field in registers FLASHA1CR2 through FLASHB2CR2. The default
+        corresponds to the reset value of the register field.

dts/bindings/mtd/nxp,imx-flexspi-hyperflash.yaml

@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI HyperFlash
+
+compatible: "nxp,imx-flexspi-hyperflash"
+
+include: nxp,imx-flexspi-device.yaml

dts/bindings/mtd/nxp,imx-flexspi-nor.yaml

@@ -0,0 +1,8 @@
+# Copyright 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP FlexSPI NOR
+
+compatible: "nxp,imx-flexspi-nor"
+
+include: nxp,imx-flexspi-device.yaml

dts/bindings/spi/nxp,imx-flexspi.yaml

@@ -13,3 +13,55 @@ properties:
 
     interrupts:
       required: true
+
+    ahb-bufferable:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB bufferable write access by setting register field
+        AHBCR[BUFFERABLEEN].
+
+    ahb-cacheable:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB cacheable read access by setting register field
+        AHBCR[CACHEABLEEN].
+
+    ahb-prefetch:
+      type: boolean
+      required: false
+      description: |
+        Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
+
+    ahb-read-addr-opt:
+      type: boolean
+      required: false
+      description: |
+        Remove burst start address alignment limitation by setting register
+        field AHBCR[READADDROPT].
+
+    combination-mode:
+      type: boolean
+      required: false
+      description: |
+        Combine port A and port B data pins to support octal mode access by
+        setting register field MCR0[COMBINATIONEN].
+
+    rx-clock-source:
+      type: int
+      required: false
+      default: 0
+      enum:
+        - 0 # Loopback internally
+        - 1 # Loopback from DQS pad
+        - 2 # Loopback from SCK pad
+        - 3 # External input from DQS pad
+      description: |
+        Source clock for flash read. See the RXCLKSRC field in register MCR0.
+        The default corresponds to the reset value of the register field.
+
+child-binding:
+    description: NXP FlexSPI port
+
+    include: nxp,imx-flexspi-device.yaml