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zephyr: bulk update to DT_NODE_HAS_STATUS_OKAY

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Change instances of:

DT_NODE_HAS_STATUS(<node_id>, okay)

to

DT_NODE_HAS_STATUS_OKAY(<node_id>)

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit is contained in:
Yong Cong Sin 2024-09-20 12:47:40 +08:00 • committed by Fabio Baltieri
commit 52a202309b
180 changed files with 743 additions and 738 deletions
Download patch file Download diff file Expand all files Collapse all files

86
soc/nxp/imx/imx6sx/soc.c
View file

@ -23,55 +23,55 @@ static void SOC_RdcInit(void)
RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1))
/* Set access to UART_1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart1, RDC_DT_VAL(uart1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
/* Set access to UART_2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))
/* Set access to UART_3 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart3, RDC_DT_VAL(uart3), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4))
/* Set access to UART_4 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart4, RDC_DT_VAL(uart4), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart5), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart5))
/* Set access to UART_5 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart6), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart6))
/* Set access to UART_6 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
/* Set access to GPIO_1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
/* Set access to GPIO_2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
/* Set access to GPIO_3 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio3, RDC_DT_VAL(gpio3), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
/* Set access to GPIO_4 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio4, RDC_DT_VAL(gpio4), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio5))
/* Set access to GPIO_5 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio6))
/* Set access to GPIO_6 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio6, RDC_DT_VAL(gpio6), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio7))
/* Set access to GPIO_7 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
#endif
@ -81,69 +81,69 @@ static void SOC_RdcInit(void)
RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false);
#endif /* CONFIG_IPM_IMX */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(epit1))
/* Set access to EPIT_1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapEpit1, RDC_DT_VAL(epit1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(epit2))
/* Set access to EPIT_2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapEpit2, RDC_DT_VAL(epit2), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
/* Set access to I2C-1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c2))
/* Set access to I2C-2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c3))
/* Set access to I2C-3 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c4))
/* Set access to I2C-4 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm1))
/* Set access to PWM-1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm2))
/* Set access to PWM-2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm3))
/* Set access to PWM-3 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm4))
/* Set access to PWM-4 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm5), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm5))
/* Set access to PWM-5 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm5, RDC_DT_VAL(pwm5), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm6), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm6))
/* Set access to PWM-6 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm6, RDC_DT_VAL(pwm6), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm7), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm7))
/* Set access to PWM-7 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm7, RDC_DT_VAL(pwm7), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm8), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm8))
/* Set access to PWM-8 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapPwm8, RDC_DT_VAL(pwm8), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc1))
/* Set access to ADC-1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapAdc1, RDC_DT_VAL(adc1), false, false);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc2))
/* Set access to ADC-2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapAdc2, RDC_DT_VAL(adc2), false, false);
#endif
@ -213,10 +213,10 @@ static void SOC_ClockInit(void)
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
/* Enable EPIT clocks */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(epit1))
CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(epit2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(epit2))
CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll);
#endif
#endif /* CONFIG_COUNTER_IMX_EPIT */
@ -229,16 +229,16 @@ static void SOC_ClockInit(void)
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
/* Enable I2C clock */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
CCM_ControlGate(CCM, ccmCcgrGateI2c1Serialclk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c2))
CCM_ControlGate(CCM, ccmCcgrGateI2c2Serialclk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c3))
CCM_ControlGate(CCM, ccmCcgrGateI2c3Serialclk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c4))
CCM_ControlGate(CCM, ccmCcgrGateI2c4Serialclk, ccmClockNeededAll);
#endif
#endif /* CONFIG_I2C_IMX */
@ -251,28 +251,28 @@ static void SOC_ClockInit(void)
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
/* Enable PWM clock */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm1))
CCM_ControlGate(CCM, ccmCcgrGatePwm1Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm2))
CCM_ControlGate(CCM, ccmCcgrGatePwm2Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm3))
CCM_ControlGate(CCM, ccmCcgrGatePwm3Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm4))
CCM_ControlGate(CCM, ccmCcgrGatePwm4Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm5), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm5))
CCM_ControlGate(CCM, ccmCcgrGatePwm5Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm6), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm6))
CCM_ControlGate(CCM, ccmCcgrGatePwm6Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm7), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm7))
CCM_ControlGate(CCM, ccmCcgrGatePwm7Clk, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm8), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm8))
CCM_ControlGate(CCM, ccmCcgrGatePwm8Clk, ccmClockNeededAll);
#endif
#endif /* CONFIG_PWM_IMX */

26
soc/nxp/imx/imx7d/soc.c
View file

@ -57,21 +57,21 @@ void SOC_RdcInit(void)
static void nxp_mcimx7_gpio_config(void)
{
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false);
/* Enable gpio clock gate */
CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false);
/* Enable gpio clock gate */
CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio7))
RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false);
/* Enable gpio clock gate */
CCM_ControlGate(CCM, ccmCcgrGateGpio7, ccmClockNeededRunWait);
@ -84,7 +84,7 @@ static void nxp_mcimx7_gpio_config(void)
static void nxp_mcimx7_uart_config(void)
{
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
/* We need to grasp board uart exclusively */
RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false);
/* Select clock derived from OSC clock(24M) */
@ -99,7 +99,7 @@ static void nxp_mcimx7_uart_config(void)
CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart6), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart6))
/* We need to grasp board uart exclusively */
RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false);
/* Select clock derived from OSC clock(24M) */
@ -121,7 +121,7 @@ static void nxp_mcimx7_uart_config(void)
static void nxp_mcimx7_i2c_config(void)
{
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c1))
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false);
/* Select I2C clock derived from OSC clock(24M) */
@ -131,7 +131,7 @@ static void nxp_mcimx7_i2c_config(void)
CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c2))
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false);
/* Select I2C clock derived from OSC clock(24M) */
@ -141,7 +141,7 @@ static void nxp_mcimx7_i2c_config(void)
CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c3))
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false);
/* Select I2C clock derived from OSC clock(24M) */
@ -151,7 +151,7 @@ static void nxp_mcimx7_i2c_config(void)
CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c4))
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false);
/* Select I2C clock derived from OSC clock(24M) */
@ -168,7 +168,7 @@ static void nxp_mcimx7_i2c_config(void)
static void nxp_mcimx7_pwm_config(void)
{
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm1))
/* We need to grasp board pwm exclusively */
RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false);
/* Select clock derived from OSC clock(24M) */
@ -178,7 +178,7 @@ static void nxp_mcimx7_pwm_config(void)
CCM_ControlGate(CCM, ccmCcgrGatePwm1, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm2))
/* We need to grasp board pwm exclusively */
RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false);
/* Select clock derived from OSC clock(24M) */
@ -188,7 +188,7 @@ static void nxp_mcimx7_pwm_config(void)
CCM_ControlGate(CCM, ccmCcgrGatePwm2, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm3))
/* We need to grasp board pwm exclusively */
RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false);
/* Select clock derived from OSC clock(24M) */
@ -198,7 +198,7 @@ static void nxp_mcimx7_pwm_config(void)
CCM_ControlGate(CCM, ccmCcgrGatePwm3, ccmClockNeededAll);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pwm4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm4))
/* We need to grasp board pwm exclusively */
RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false);
/* Select clock derived from OSC clock(24M) */

8
soc/nxp/imx/imx8m/a53/soc.c
View file

@ -12,7 +12,7 @@
#include <fsl_common.h>
#include <fsl_rdc.h>
#if DT_NODE_HAS_STATUS(DT_NODELABEL(rdc), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(rdc))
#define rdc_inst ((RDC_Type *)DT_REG_ADDR(DT_NODELABEL(rdc)))
@ -28,19 +28,19 @@ static void soc_rdc_init(void)
RDC_GetDefaultPeriphAccessConfig(&periphConfig);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(uart2), rdc)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) && DT_NODE_HAS_PROP(DT_NODELABEL(uart2), rdc)
periphConfig.periph = kRDC_Periph_UART2;
periphConfig.policy = RDC_DT_VAL(uart2);
RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(uart4), rdc)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4)) && DT_NODE_HAS_PROP(DT_NODELABEL(uart4), rdc)
periphConfig.periph = kRDC_Periph_UART4;
periphConfig.policy = RDC_DT_VAL(uart4);
RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && DT_NODE_HAS_PROP(DT_NODELABEL(enet), rdc)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && DT_NODE_HAS_PROP(DT_NODELABEL(enet), rdc)
periphConfig.periph = kRDC_Periph_ENET1;
periphConfig.policy = RDC_DT_VAL(enet);
RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);

8
soc/nxp/imx/imx8m/m4_mini/soc.c
View file

@ -104,25 +104,25 @@ static void SOC_ClockInit(void)
CLOCK_SetRootMux(kCLOCK_RootAudioAhb, kCLOCK_AudioAhbRootmuxSysPll1);
#if defined(CONFIG_UART_MCUX_IUART)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */

8
soc/nxp/imx/imx8m/m4_quad/soc.c
View file

@ -67,25 +67,25 @@ static void SOC_ClockInit(void)
CLOCK_SetRootMux(kCLOCK_RootM4, kCLOCK_M4RootmuxSysPll1Div3);
#if defined(CONFIG_UART_MCUX_IUART)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */

24
soc/nxp/imx/imx8m/m7/soc.c
View file

@ -107,25 +107,25 @@ static void SOC_ClockInit(void)
CLOCK_SetRootMux(kCLOCK_RootAhb, kCLOCK_AhbRootmuxSysPll1Div6);
#if defined(CONFIG_UART_MCUX_IUART)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart1, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart1, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart2, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart2, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart3, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootUart3, 1U, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4))
/* Set UART source to SysPLL1 Div10 80MHZ */
CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10);
/* Set root clock to 80MHZ/ 1= 80MHZ */
@ -134,21 +134,21 @@ static void SOC_ClockInit(void)
#endif
#if defined(CONFIG_SPI_MCUX_ECSPI)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ecspi1))
/* Set ECSPI1 source to SYSTEM PLL1 800MHZ */
CLOCK_SetRootMux(kCLOCK_RootEcspi1, kCLOCK_EcspiRootmuxSysPll1);
/* Set root clock to 800MHZ / 10 = 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootEcspi1, 2U, 5U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ecspi2))
/* Set ECSPI2 source to SYSTEM PLL1 800MHZ */
CLOCK_SetRootMux(kCLOCK_RootEcspi2, kCLOCK_EcspiRootmuxSysPll1);
/* Set root clock to 800MHZ / 10 = 80MHZ */
CLOCK_SetRootDivider(kCLOCK_RootEcspi2, 2U, 5U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ecspi3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ecspi3))
/* Set ECSPI3 source to SYSTEM PLL1 800MHZ */
CLOCK_SetRootMux(kCLOCK_RootEcspi3, kCLOCK_EcspiRootmuxSysPll1);
/* Set root clock to 800MHZ / 10 = 80MHZ */
@ -175,27 +175,27 @@ static void gpio_init(void)
{
#if defined(CONFIG_GPIO_MCUX_IGPIO)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
CLOCK_EnableClock(kCLOCK_Gpio1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
CLOCK_EnableClock(kCLOCK_Gpio2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
CLOCK_EnableClock(kCLOCK_Gpio3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
CLOCK_EnableClock(kCLOCK_Gpio4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio5))
CLOCK_EnableClock(kCLOCK_Gpio5);

2
soc/nxp/imxrt/imxrt10xx/flexspi.c
View file

@ -28,7 +28,7 @@ uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate)
div_sel = kCLOCK_FlexspiDiv;
clk_name = kCLOCK_FlexSpi;
break;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi2))
case IMX_CCM_FLEXSPI2_CLK:
/* Get clock root frequency */
root_rate = CLOCK_GetClockRootFreq(kCLOCK_Flexspi2ClkRoot) *

24
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -67,10 +67,10 @@ const clock_enet_pll_config_t ethPllConfig = {
.enableClkOutput500M = true,
#endif
#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
.enableClkOutput = true,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2))
.enableClkOutput1 = true,
#endif
#endif
@ -79,10 +79,10 @@ const clock_enet_pll_config_t ethPllConfig = {
#else
.enableClkOutput25M = false,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
.loopDivider = 1,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2))
.loopDivider1 = 1,
#endif
};
@ -226,7 +226,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && CONFIG_NET_L2_ETHERNET
#if CONFIG_ETH_MCUX_RMII_EXT_CLK
/* Enable clock input for ENET1 */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false);
@ -236,43 +236,43 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2)) && CONFIG_NET_L2_ETHERNET
/* Set ENET2 ref clock to be generated by External OSC,*/
/* direction as output and frequency to 50MHz */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir |
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && \
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && \
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc1)) && CONFIG_IMX_USDHC
/* Configure USDHC clock source and divider */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc2)) && CONFIG_IMX_USDHC
/* Configure USDHC clock source and divider */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U);

36
soc/nxp/imxrt/imxrt118x/soc.c
View file

@ -208,16 +208,16 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if defined(CONFIG_UART_MCUX_LPUART) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2)))
/* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 10;
#endif
#if defined(CONFIG_I2C_MCUX_LPI2C) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c2), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)))
/* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 4;
@ -225,8 +225,8 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if defined(CONFIG_I2C_MCUX_LPI2C) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c3), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c4), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c4)))
/* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 4;
@ -234,8 +234,8 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if defined(CONFIG_I2C_MCUX_LPI2C) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c5), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c6), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c5)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c6)))
/* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 4;
@ -243,8 +243,8 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if defined(CONFIG_SPI_MCUX_LPSPI) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi2), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi2)))
/* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
rootCfg.div = 2;
@ -253,28 +253,28 @@ static ALWAYS_INLINE void clock_init(void)
#if defined(CONFIG_COUNTER_MCUX_GPT)
#if (DT_NODE_HAS_STATUS(DT_NODELABEL(gpt1), okay))
#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)))
/* Configure GPT1 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpt1), okay) */
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)) */
#if (DT_NODE_HAS_STATUS(DT_NODELABEL(gpt2), okay))
#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt2)))
/* Configure GPT2 using SYS_PLL3_DIV2_CLK */
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpt2), okay) */
#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt2)) */
#endif /* CONFIG_COUNTER_MCUX_GPT */
#ifdef CONFIG_MCUX_ACMP
#if (DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(acmp2), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(acmp3), okay) \
|| DT_NODE_HAS_STATUS(DT_NODELABEL(acmp4), okay))
#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp2)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp3)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp4)))
/* Configure ACMP using MuxSysPll3Out */
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;

24
soc/nxp/imxrt/imxrt11xx/soc.c
View file

@ -409,7 +409,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
/* 50 MHz ENET clock */
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
rootCfg.div = 10;
@ -424,7 +424,7 @@ static ALWAYS_INLINE void clock_init(void)
(IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U));
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet1g))
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2;
#if DT_ENUM_HAS_VALUE(DT_CHILD(DT_NODELABEL(enet1g), ethernet), phy_connection_type, rgmii)
/* 125 MHz ENET1G clock */
@ -491,13 +491,13 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#ifdef CONFIG_CAN_MCUX_FLEXCAN
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1))
/* Configure CAN1 using Osc48MDiv2 */
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan3))
/* Configure CAN1 using Osc48MDiv2 */
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
@ -506,7 +506,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#ifdef CONFIG_MCUX_ACMP
#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1))
/* Configure ACMP1 using Osc48MDiv2*/
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
@ -532,28 +532,28 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs0PhyPllClock(
kCLOCK_Usb480M, DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs1PhyPllClock(
kCLOCK_Usb480M, DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if CONFIG_IMX_USDHC
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc1))
/* Configure USDHC1 using SysPll2Pfd2*/
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2;
rootCfg.div = 2;
@ -561,7 +561,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc2))
/* Configure USDHC2 using SysPll2Pfd2*/
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2;
rootCfg.div = 2;
@ -571,7 +571,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif
#if !(DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), nxp_imx_flexspi)) && \
defined(CONFIG_MEMC_MCUX_FLEXSPI) && DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay)
defined(CONFIG_MEMC_MCUX_FLEXSPI) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi))
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;

4
soc/nxp/imxrt/imxrt5xx/cm33/soc.c
View file

@ -358,7 +358,7 @@ void __weak rt5xx_clock_init(void)
/* Switch CLKOUT to FRO_DIV2 */
CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) && CONFIG_IMX_USDHC
/* Make sure USDHC ram buffer has been power up*/
POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM);
POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM);
@ -373,7 +373,7 @@ void __weak rt5xx_clock_init(void)
RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(smartdma), okay) && CONFIG_DMA_MCUX_SMARTDMA
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(smartdma)) && CONFIG_DMA_MCUX_SMARTDMA
/* Power up SMARTDMA ram */
POWER_DisablePD(kPDRUNCFG_APD_SMARTDMA_SRAM);
POWER_DisablePD(kPDRUNCFG_PPD_SMARTDMA_SRAM);

4
soc/nxp/imxrt/imxrt6xx/cm33/soc.c
View file

@ -286,7 +286,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_AttachClk(kNONE_to_WDT0_CLK);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) && CONFIG_IMX_USDHC
/* Make sure USDHC ram buffer has been power up*/
POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM);
POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM);
@ -350,7 +350,7 @@ static ALWAYS_INLINE void clock_init(void)
#endif /* CONFIG_SOC_MIMXRT685S_CM33 */
}
#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC)
#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) && CONFIG_IMX_USDHC)
void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, uint32_t speed, uint32_t strength)
{

4
soc/nxp/imxrt/imxrt6xx/cm33/soc.h
View file

@ -85,8 +85,8 @@ extern "C" {
#endif
#if CONFIG_IMX_USDHC && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc1)))
void imxrt_usdhc_pinmux(uint16_t nusdhc,
bool init, uint32_t speed, uint32_t strength);

2
soc/nxp/kinetis/k6x/soc.c
View file

@ -101,7 +101,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetSimConfig(&simConfig);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK);
#endif

32
soc/nxp/kinetis/ke1xf/soc.c
View file

@ -61,7 +61,7 @@ static const scg_sys_clk_config_t scg_sys_clk_config = {
#endif
};
#if DT_NODE_HAS_STATUS(SCG_CLOCK_NODE(sosc_clk), okay)
#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
/* System Oscillator (SOSC) configuration */
ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv1_clk),
"Invalid SCG SOSC divider 1 value");
@ -155,7 +155,7 @@ static ALWAYS_INLINE void clk_init(void)
};
scg_sys_clk_config_t current;
#if DT_NODE_HAS_STATUS(SCG_CLOCK_NODE(sosc_clk), okay)
#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
/* Optionally initialize system oscillator */
CLOCK_InitSysOsc(&scg_sosc_config);
CLOCK_SetXtal0Freq(scg_sosc_config.freq);
@ -179,59 +179,59 @@ static ALWAYS_INLINE void clk_init(void)
CLOCK_GetCurSysClkConfig(&current);
} while (current.src != scg_sys_clk_config.src);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
CLOCK_SetIpSrc(kCLOCK_Lpuart0,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
CLOCK_SetIpSrc(kCLOCK_Lpuart1,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
CLOCK_SetIpSrc(kCLOCK_Lpuart2,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart2), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0))
CLOCK_SetIpSrc(kCLOCK_Lpi2c0,
DT_CLOCKS_CELL(DT_NODELABEL(lpi2c0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1))
CLOCK_SetIpSrc(kCLOCK_Lpi2c1,
DT_CLOCKS_CELL(DT_NODELABEL(lpi2c1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0))
CLOCK_SetIpSrc(kCLOCK_Lpspi0,
DT_CLOCKS_CELL(DT_NODELABEL(lpspi0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1))
CLOCK_SetIpSrc(kCLOCK_Lpspi1,
DT_CLOCKS_CELL(DT_NODELABEL(lpspi1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc0))
CLOCK_SetIpSrc(kCLOCK_Adc0,
DT_CLOCKS_CELL(DT_NODELABEL(adc0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc1))
CLOCK_SetIpSrc(kCLOCK_Adc1,
DT_CLOCKS_CELL(DT_NODELABEL(adc1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc2))
CLOCK_SetIpSrc(kCLOCK_Adc2,
DT_CLOCKS_CELL(DT_NODELABEL(adc2), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ftm0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm0))
CLOCK_SetIpSrc(kCLOCK_Ftm0,
DT_CLOCKS_CELL(DT_NODELABEL(ftm0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ftm1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm1))
CLOCK_SetIpSrc(kCLOCK_Ftm1,
DT_CLOCKS_CELL(DT_NODELABEL(ftm1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ftm2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm2))
CLOCK_SetIpSrc(kCLOCK_Ftm2,
DT_CLOCKS_CELL(DT_NODELABEL(ftm2), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ftm3), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ftm3))
CLOCK_SetIpSrc(kCLOCK_Ftm3,
DT_CLOCKS_CELL(DT_NODELABEL(ftm3), ip_source));
#endif

18
soc/nxp/kinetis/ke1xz/soc.c
View file

@ -106,39 +106,39 @@ static ALWAYS_INLINE void clk_init(void)
CLOCK_GetCurSysClkConfig(&current);
} while (current.src != scg_sys_clk_config.src);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
CLOCK_SetIpSrc(kCLOCK_Lpuart0,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
CLOCK_SetIpSrc(kCLOCK_Lpuart1,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
CLOCK_SetIpSrc(kCLOCK_Lpuart2,
DT_CLOCKS_CELL(DT_NODELABEL(lpuart2), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0))
CLOCK_SetIpSrc(kCLOCK_Lpi2c0,
DT_CLOCKS_CELL(DT_NODELABEL(lpi2c0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1))
CLOCK_SetIpSrc(kCLOCK_Lpi2c1,
DT_CLOCKS_CELL(DT_NODELABEL(lpi2c1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio))
CLOCK_SetIpSrc(kCLOCK_Flexio0,
DT_CLOCKS_CELL(DT_NODELABEL(flexio), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0))
CLOCK_SetIpSrc(kCLOCK_Lpspi0,
DT_CLOCKS_CELL(DT_NODELABEL(lpspi0), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1))
CLOCK_SetIpSrc(kCLOCK_Lpspi1,
DT_CLOCKS_CELL(DT_NODELABEL(lpspi1), ip_source));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(adc0))
CLOCK_SetIpSrc(kCLOCK_Adc0,
DT_CLOCKS_CELL(DT_NODELABEL(adc0), ip_source));
#endif

2
soc/nxp/kinetis/kl2x/soc.c
View file

@ -70,7 +70,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0);
CLOCK_SetSimConfig(&simConfig);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart0))
CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK);
#endif
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS

8
soc/nxp/kinetis/kwx/soc_kw4xz.c
View file

@ -67,14 +67,14 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_SetSimConfig(&simConfig);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK);
#endif
#if defined(CONFIG_PWM) && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(pwm0), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(pwm1), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(pwm2), okay))
(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm0)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm1)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pwm2)))
CLOCK_SetTpmClock(TPMSRC_MCGPLLCLK);
#endif
}

2
soc/nxp/lpc/lpc55xxx/soc.c
View file

@ -193,7 +193,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(hs_lspi), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(hs_lspi))
/* Attach 12 MHz clock to HSLSPI */
CLOCK_AttachClk(kFRO_HF_DIV_to_HSLSPI);
#endif

2
soc/nxp/mcx/mcxc/soc.c
View file

@ -95,7 +95,7 @@ static void clock_init(void)
/* Set SystemCoreClock variable. */
SystemCoreClock = DT_PROP(DT_NODELABEL(cpu0), clock_frequency);
/* Set LPUART0 clock source. */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
CLOCK_SetLpuart0Clock(LPUART_CLOCK_SEL(lpuart0));
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_tpm)

14
soc/nxp/rw/power.c
View file

@ -28,11 +28,11 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
power_sleep_config_t slp_cfg;
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay) || DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
pinctrl_soc_pin_t pin_cfg;
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0))
static void pin0_isr(const struct device *dev)
{
uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin0), wakeup_level)) & 0x1;
@ -44,7 +44,7 @@ static void pin0_isr(const struct device *dev)
}
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
static void pin1_isr(const struct device *dev)
{
uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin1), wakeup_level)) & 0x1;
@ -61,7 +61,7 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0))
pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO);
pinctrl_configure_pins(&pin_cfg, 1, 0);
POWER_ConfigWakeupPin(kPOWER_WakeupPin0, DT_ENUM_IDX(DT_NODELABEL(pin0), wakeup_level));
@ -70,7 +70,7 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
EnableIRQ(DT_IRQN(DT_NODELABEL(pin0)));
POWER_EnableWakeup(DT_IRQN(DT_NODELABEL(pin0)));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO);
pinctrl_configure_pins(&pin_cfg, 1, 0);
POWER_ConfigWakeupPin(kPOWER_WakeupPin1, DT_ENUM_IDX(DT_NODELABEL(pin1), wakeup_level));
@ -119,7 +119,7 @@ void nxp_rw6xx_power_init(void)
slp_cfg.memPdCfg = suspend_sleepconfig[3];
slp_cfg.pm3BuckCfg = suspend_sleepconfig[4];
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin0), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0))
/* PIN 0 uses GPIO0_24, confiure the pin as GPIO */
pin_cfg = IOMUX_GPIO_IDX(24) | IOMUX_TYPE(IOMUX_GPIO);
pinctrl_configure_pins(&pin_cfg, 1, 0);
@ -131,7 +131,7 @@ void nxp_rw6xx_power_init(void)
NULL, 0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pin1), okay)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
/* PIN 1 uses GPIO0_25, confiure the pin as GPIO */
pin_cfg = IOMUX_GPIO_IDX(25) | IOMUX_TYPE(IOMUX_GPIO);
pinctrl_configure_pins(&pin_cfg, 1, 0);

10
soc/nxp/rw/soc.c
View file

@ -221,7 +221,7 @@ __ramfunc void clock_init(void)
#endif
#endif /* CONFIG_SPI */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(dmic0), okay) && CONFIG_AUDIO_DMIC_MCUX
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dmic0)) && CONFIG_AUDIO_DMIC_MCUX
/* Clock DMIC from Audio PLL. PLL output is sourced from AVPLL
* channel 1, which is clocked at 12.288 MHz. We can divide this
* by 4 to achieve the desired DMIC bit clk of 3.072 MHz
@ -230,7 +230,7 @@ __ramfunc void clock_init(void)
CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lcdic), okay) && CONFIG_MIPI_DBI_NXP_LCDIC
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lcdic)) && CONFIG_MIPI_DBI_NXP_LCDIC
CLOCK_AttachClk(kMAIN_CLK_to_LCD_CLK);
RESET_PeripheralReset(kLCDIC_RST_SHIFT_RSTn);
#endif
@ -250,7 +250,7 @@ __ramfunc void clock_init(void)
#endif
#endif /* CONFIG_COUNTER_MCUX_CTIMER */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb_otg), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb_otg)) && CONFIG_USB_DC_NXP_EHCI
/* Enable system xtal from Analog */
SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK;
/* reset USB */
@ -261,7 +261,7 @@ __ramfunc void clock_init(void)
CLOCK_EnableUsbhsPhyClock();
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && CONFIG_NET_L2_ETHERNET
RESET_PeripheralReset(kENET_IPG_RST_SHIFT_RSTn);
RESET_PeripheralReset(kENET_IPG_S_RST_SHIFT_RSTn);
#endif
@ -289,7 +289,7 @@ void soc_early_init_hook(void)
#define PMU_RESET_CAUSES \
COND_CODE_0(IS_EMPTY(PMU_RESET_CAUSES_), (PMU_RESET_CAUSES_), (0))
#define WDT_RESET \
COND_CODE_1(DT_NODE_HAS_STATUS(wwdt, okay), (kPOWER_ResetSourceWdt), (0))
COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(wwdt), (kPOWER_ResetSourceWdt), (0))
#define RESET_CAUSES \
(PMU_RESET_CAUSES | WDT_RESET)
#else