Revert "arch: xtensa: Use reset-vector.S in booloader code"
This reverts commit 9987c2e2f9
which spills SoC configs into architecture files and is not
exactly desirable. So revert it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
parent
db2eb23bd2
commit
52993afd62
1 changed files with 5 additions and 64 deletions
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@ -13,10 +13,6 @@
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#include <xtensa/config/system.h> /* for XSHAL_USE_ABSOLUTE_LITERALS only */
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#include <xtensa/xtruntime-core-state.h>
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#if defined(BOOTLOADER)
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#include <platform/memory.h>
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#endif
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/*
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* The following reset vector avoids initializing certain registers already
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* initialized by processor reset. But it does initialize some of them
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@ -28,13 +24,8 @@
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.section .ResetVector.text, "ax"
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.align 4
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#if defined(BOOTLOADER)
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.global _ResetVector
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_ResetVector:
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#else
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.global __start
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__start:
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#endif
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#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
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/*
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@ -45,55 +36,16 @@ __start:
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* the reset vector's 'j' instruction, the _ResetHandler symbol
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* and a more elaborate j/movi/jx sequence are needed in
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* .ResetVector.text to dispatch to the new location.
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*
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* If we have dynamic cache way support, init the caches as soon
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* as we can, which is now. Except, if we are waking up from a
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* PSO event, then we need to do this slightly later.
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*/
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#if defined(BOOTLOADER)
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#if XCHAL_USE_MEMCTL
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#if XCHAL_HAVE_PSO_CDM && !XCHAL_HAVE_PSO_FULL_RETENTION
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/* Do this later on in the code -- see below */
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#else
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movi a0, ~MEMCTL_SNOOP_EN
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wsr a0, MEMCTL
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#endif
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#endif
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#endif /* BOOTLOADER */
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#if defined(BOOTLOADER)
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/* This is our VM bxt ROM. It simply jumps to the reset handler. */
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j .sram_jump /* jump over the literals */
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.align 4
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.literal_position /* tells the assembler/linker to place
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* literals here
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*/
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_reset_sram:
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.word _ResetHandler
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.align 4
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.sram_jump:
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l32r a0, _reset_sram /* load SRAM reset handler address */
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jx a0 /* jump to the hanlder */
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.size _ResetVector, . - _ResetVector
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#endif /* BOOTLOADER */
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j _ResetHandler
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#if defined(BOOTLOADER)
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.size _ResetVector, . - _ResetVector
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#else
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.size __start, . - __start
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#endif
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#if XCHAL_HAVE_HALT
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/*
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* Xtensa TX: reset vector segment is only 4 bytes, so must place the
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* unpacker code elsewhere in the memory that contains the reset
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* vector.
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* Xtensa TX: reset vector segment is only 4 bytes, so must place the
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* unpacker code elsewhere in the memory that contains the reset
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* vector.
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*/
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#if XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTRAM0_VADDR
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.section .iram0.text, "ax"
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@ -115,7 +67,6 @@ _reset_sram:
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.literal_position
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.align 4
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.global _ResetHandler
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_ResetHandler:
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#endif
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@ -327,7 +278,6 @@ _ResetHandler:
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s32i a0, a2, 0 /* clear sync variable */
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.Ldonesync:
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#endif
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#if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MP_RUNSTALL
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/* On core 0, this releases other cores. On other cores this has no
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* effect, because runstall control is unconnected
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@ -638,6 +588,7 @@ unpackdone:
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# endif
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#endif /* pre-LX2 */
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/*
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* Initialize memory error handler address.
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* Putting this address in a register allows multiple instances of
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@ -646,7 +597,7 @@ unpackdone:
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* it is not VECBASE relative) to have the same memory error vector,
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* yet each have their own handler and associated data save area.
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*/
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#if XCHAL_HAVE_MEM_ECC_PARITY_IGNORE
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#if XCHAL_HAVE_MEM_ECC_PARITY
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movi a4, _MemErrorHandler
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wsr a4, MESAVE
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#endif
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@ -709,13 +660,7 @@ unpackdone:
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* -mlongcalls) which it doesn't with j or jx. Note: This needs to
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* be call0 regardless of the selected ABI.
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*/
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#if defined(BOOTLOADER)
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/*ToDo refine the _start*/
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movi a0, SOF_TEXT_BASE
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callx0 a0
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#else
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call0 _start /* jump to _start (in crt1-*.S) */
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#endif
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/* does not return */
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#else /* XCHAL_HAVE_HALT */
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@ -740,12 +685,8 @@ unpackdone:
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#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE
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.size _ResetHandler, . - _ResetHandler
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#else
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#if defined(BOOTLOADER)
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.size _ResetVector, . - _ResetVector
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#else
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.size __start, . - __start
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#endif
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#endif
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.text
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