clock_control: RV32M1: introduce PCC driver / DT bindings

Add a Peripheral Clock Controller (PCC) driver. This gates and ungates
clocks to various peripherals on the SoC.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>

drivers/clock_control/CMakeLists.txt

@@ -3,6 +3,7 @@ zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM            clock_control_mcux
 zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM            clock_control_mcux_sim.c)
 zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF                 nrf_power_clock.c)
 zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_QUARK_SE            quark_se_clock_control.c)
+zephyr_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
   zephyr_sources(stm32_ll_clock.c)

drivers/clock_control/Kconfig

@@ -35,4 +35,6 @@ source "drivers/clock_control/Kconfig.mcux_ccm"
 
 source "drivers/clock_control/Kconfig.mcux_sim"
 
+source "drivers/clock_control/Kconfig.rv32m1"
+
 endif # CLOCK_CONTROL

drivers/clock_control/Kconfig.rv32m1

@@ -0,0 +1,12 @@
+# Kconfig - OpenISA RV32M1 PPC
+#
+# Copyright (c) 2018 Foundries.io
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig CLOCK_CONTROL_RV32M1_PCC
+	bool "RV32M1 PCC driver"
+	depends on SOC_OPENISA_RV32M1_RISCV32
+	help
+	  Enable support for RV32M1 PCC driver.

drivers/clock_control/clock_control_rv32m1_pcc.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018 Foundries.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <errno.h>
+#include <soc.h>
+#include <clock_control.h>
+#include <fsl_clock.h>
+
+#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
+#include <logging/log.h>
+LOG_MODULE_REGISTER(clock_control);
+
+struct rv32m1_pcc_config {
+	u32_t base_address;
+};
+
+#define DEV_CFG(dev)  ((struct rv32m1_pcc_config *)(dev->config->config_info))
+#define DEV_BASE(dev) (DEV_CFG(dev)->base_address)
+
+static inline clock_ip_name_t clock_ip(struct device *dev,
+				       clock_control_subsys_t sub_system)
+{
+	u32_t offset = POINTER_TO_UINT(sub_system);
+
+	return MAKE_PCC_REGADDR(DEV_BASE(dev), offset);
+}
+
+static int rv32m1_pcc_on(struct device *dev, clock_control_subsys_t sub_system)
+{
+	CLOCK_EnableClock(clock_ip(dev, sub_system));
+	return 0;
+}
+
+static int rv32m1_pcc_off(struct device *dev, clock_control_subsys_t sub_system)
+{
+	CLOCK_DisableClock(clock_ip(dev, sub_system));
+	return 0;
+}
+
+static int rv32m1_pcc_get_rate(struct device *dev,
+			       clock_control_subsys_t sub_system,
+			       u32_t *rate)
+{
+	*rate = CLOCK_GetIpFreq(clock_ip(dev, sub_system));
+	return 0;
+}
+
+static int rv32m1_pcc_init(struct device *dev)
+{
+	return 0;
+}
+
+static const struct clock_control_driver_api rv32m1_pcc_api = {
+	.on = rv32m1_pcc_on,
+	.off = rv32m1_pcc_off,
+	.get_rate = rv32m1_pcc_get_rate,
+};
+
+#if defined(PCC_0_BASE_ADDRESS)
+static struct rv32m1_pcc_config rv32m1_pcc0_config = {
+	.base_address = PCC_0_BASE_ADDRESS
+};
+
+DEVICE_AND_API_INIT(rv32m1_pcc0, PCC_0_LABEL,
+		    &rv32m1_pcc_init,
+		    NULL, &rv32m1_pcc0_config,
+		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
+		    &rv32m1_pcc_api);
+#endif
+
+#if defined(PCC_1_BASE_ADDRESS)
+static struct rv32m1_pcc_config rv32m1_pcc1_config = {
+	.base_address = PCC_1_BASE_ADDRESS
+};
+
+DEVICE_AND_API_INIT(rv32m1_pcc1, PCC_1_LABEL,
+		    &rv32m1_pcc_init,
+		    NULL, &rv32m1_pcc1_config,
+		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
+		    &rv32m1_pcc_api);
+#endif

dts/bindings/riscv/openisa,rv32m1-pcc.yaml

@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2018 Foundries.io
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: RV32M1 PCC (Peripheral Clock Control)
+version: 0.1
+
+description: >
+    This is a representation of the RV32M1 PCC IP node
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "openisa,rv32m1-pcc"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+"#cells":
+  - name
+  - offset
+...

dts/riscv32/rv32m1_ri5cy.dtsi

@@ -7,6 +7,11 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	aliases {
+		pcc-0 = &pcc0;
+		pcc-1 = &pcc1;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -22,4 +27,27 @@
 		compatible = "mmio-sram";
 		reg = <0x20000000 0x30000>;
 	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		pcc0: clock-controller@4002b000 {
+			compatible = "openisa,rv32m1-pcc";
+			clock-controller;
+			reg = <0x4002b000 0x200>;
+			label = "PCC0";
+			#clock-cells = <1>;
+		};
+
+		pcc1: clock-controller@41027000 {
+			compatible = "openisa,rv32m1-pcc";
+			clock-controller;
+			reg = <0x41027000 0x200>;
+			label = "PCC1";
+			#clock-cells = <1>;
+		};
+	};
 };

soc/riscv32/openisa_rv32m1/Kconfig.soc

@@ -15,6 +15,7 @@ config SOC_OPENISA_RV32M1_RISCV32
 	select ATOMIC_OPERATIONS_C
 	select VEGA_SDK_HAL
 	select RISCV_SOC_INTERRUPT_INIT
+	select CLOCK_CONTROL
 	help
 	  Enable support for OpenISA RV32M1 RISC-V processors. Choose
 	  this option to target the RI5CY or ZERO-RISCY core. This