drivers: sdhc: imx_usdhc: enable MMIO mapping
Enable MMIO mapping in the driver. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan
Benjamin Cabé
parent
819125f726
commit
51e0fcf80c
1 changed files with 103 additions and 84 deletions
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@ -43,6 +43,9 @@ enum transfer_callback_status {
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/* Default transfer timeout in ms for tuning */
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#define IMX_USDHC_DEFAULT_TIMEOUT (5000U)
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#define DEV_CFG(_dev) ((const struct usdhc_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct usdhc_data *)(_dev)->data)
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struct usdhc_host_transfer {
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usdhc_transfer_t *transfer;
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k_timeout_t command_timeout;
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@ -50,7 +53,8 @@ struct usdhc_host_transfer {
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};
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struct usdhc_config {
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USDHC_Type *base;
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DEVICE_MMIO_NAMED_ROM(usdhc_mmio);
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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uint8_t nusdhc;
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@ -75,6 +79,8 @@ struct usdhc_config {
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};
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struct usdhc_data {
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DEVICE_MMIO_NAMED_RAM(usdhc_mmio);
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const struct device *dev;
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struct sdhc_host_props props;
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bool card_present;
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@ -93,6 +99,11 @@ struct usdhc_data {
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#endif
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};
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static USDHC_Type *get_base(const struct device *dev)
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{
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return (USDHC_Type *)DEVICE_MMIO_NAMED_GET(dev, usdhc_mmio);
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}
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static void transfer_complete_cb(USDHC_Type *usdhc, usdhc_handle_t *handle, status_t status,
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void *user_data)
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{
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@ -200,17 +211,17 @@ static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup)
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*/
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static void imx_usdhc_error_recovery(const struct device *dev)
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{
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const struct usdhc_config *cfg = dev->config;
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uint32_t status = USDHC_GetPresentStatusFlags(cfg->base);
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USDHC_Type *base = get_base(dev);
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uint32_t status = USDHC_GetPresentStatusFlags(base);
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if (status & kUSDHC_CommandInhibitFlag) {
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/* Reset command line */
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USDHC_Reset(cfg->base, kUSDHC_ResetCommand, 100U);
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USDHC_Reset(base, kUSDHC_ResetCommand, 100U);
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}
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if (((status & (uint32_t)kUSDHC_DataInhibitFlag) != 0U) ||
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(USDHC_GetAdmaErrorStatusFlags(cfg->base) != 0U)) {
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(USDHC_GetAdmaErrorStatusFlags(base) != 0U)) {
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/* Reset data line */
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USDHC_Reset(cfg->base, kUSDHC_DataInhibitFlag, 100U);
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USDHC_Reset(base, kUSDHC_DataInhibitFlag, 100U);
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}
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}
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@ -223,6 +234,7 @@ static void imx_usdhc_init_host_props(const struct device *dev)
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struct usdhc_data *data = dev->data;
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usdhc_capability_t caps;
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struct sdhc_host_props *props = &data->props;
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USDHC_Type *base = get_base(dev);
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memset(props, 0, sizeof(struct sdhc_host_props));
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props->f_max = cfg->max_bus_freq;
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@ -231,7 +243,7 @@ static void imx_usdhc_init_host_props(const struct device *dev)
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props->max_current_180 = cfg->max_current_180;
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props->power_delay = cfg->power_delay_ms;
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/* Read host capabilities */
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USDHC_GetCapability(cfg->base, &caps);
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USDHC_GetCapability(base, &caps);
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if (cfg->no_180_vol) {
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props->host_caps.vol_180_support = false;
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} else {
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@ -258,24 +270,25 @@ static void imx_usdhc_init_host_props(const struct device *dev)
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*/
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static int imx_usdhc_reset(const struct device *dev)
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{
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const struct usdhc_config *cfg = dev->config;
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USDHC_Type *base = get_base(dev);
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/* Switch to default I/O voltage of 3.3V */
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imx_usdhc_select_1_8v(cfg->base, false);
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USDHC_EnableDDRMode(cfg->base, false, 0U);
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imx_usdhc_select_1_8v(base, false);
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USDHC_EnableDDRMode(base, false, 0U);
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#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE)
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USDHC_EnableStandardTuning(cfg->base, 0, 0, false);
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USDHC_EnableAutoTuning(cfg->base, false);
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USDHC_EnableStandardTuning(base, 0, 0, false);
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USDHC_EnableAutoTuning(base, false);
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#endif
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#if FSL_FEATURE_USDHC_HAS_HS400_MODE
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/* Disable HS400 mode */
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USDHC_EnableHS400Mode(cfg->base, false);
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USDHC_EnableHS400Mode(base, false);
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/* Disable DLL */
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USDHC_EnableStrobeDLL(cfg->base, false);
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USDHC_EnableStrobeDLL(base, false);
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#endif
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/* Reset data/command/tuning circuit */
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return USDHC_Reset(cfg->base, kUSDHC_ResetAll, 1000U) == true ? 0 : -ETIMEDOUT;
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return USDHC_Reset(base, kUSDHC_ResetAll, 1000U) == true ? 0 : -ETIMEDOUT;
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}
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/*
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@ -287,6 +300,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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struct usdhc_data *data = dev->data;
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uint32_t src_clk_hz, bus_clk;
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struct sdhc_io *host_io = &data->host_io;
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USDHC_Type *base = get_base(dev);
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LOG_DBG("SDHC I/O: bus width %d, clock %dHz, card power %s, voltage %s", ios->bus_width,
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ios->clock, ios->power_mode == SDHC_POWER_ON ? "ON" : "OFF",
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@ -304,7 +318,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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if (host_io->clock != ios->clock) {
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if (ios->clock != 0) {
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/* Enable the clock output */
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bus_clk = USDHC_SetSdClock(cfg->base, src_clk_hz, ios->clock);
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bus_clk = USDHC_SetSdClock(base, src_clk_hz, ios->clock);
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LOG_DBG("BUS CLOCK: %d", bus_clk);
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if (bus_clk == 0) {
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return -ENOTSUP;
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@ -317,13 +331,13 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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if (host_io->bus_width != ios->bus_width) {
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switch (ios->bus_width) {
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case SDHC_BUS_WIDTH1BIT:
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USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth1Bit);
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USDHC_SetDataBusWidth(base, kUSDHC_DataBusWidth1Bit);
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break;
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case SDHC_BUS_WIDTH4BIT:
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USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth4Bit);
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USDHC_SetDataBusWidth(base, kUSDHC_DataBusWidth4Bit);
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break;
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case SDHC_BUS_WIDTH8BIT:
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USDHC_SetDataBusWidth(cfg->base, kUSDHC_DataBusWidth8Bit);
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USDHC_SetDataBusWidth(base, kUSDHC_DataBusWidth8Bit);
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break;
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default:
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return -ENOTSUP;
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@ -336,7 +350,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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switch (ios->signal_voltage) {
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case SD_VOL_3_3_V:
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case SD_VOL_3_0_V:
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imx_usdhc_select_1_8v(cfg->base, false);
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imx_usdhc_select_1_8v(base, false);
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break;
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case SD_VOL_1_8_V:
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/**
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@ -350,15 +364,15 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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* 10 ms, then allow it to be gated again.
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*/
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/* Switch to 1.8V */
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imx_usdhc_select_1_8v(cfg->base, true);
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imx_usdhc_select_1_8v(base, true);
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/* Wait 10 ms- clock will be gated during this period */
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k_msleep(10);
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/* Force the clock on */
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USDHC_ForceClockOn(cfg->base, true);
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USDHC_ForceClockOn(base, true);
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/* Keep the clock on for a moment, so SD will recognize it */
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k_msleep(10);
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/* Stop forcing clock on */
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USDHC_ForceClockOn(cfg->base, false);
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USDHC_ForceClockOn(base, false);
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break;
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default:
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return -ENOTSUP;
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@ -386,7 +400,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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case SDHC_TIMING_DDR50:
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case SDHC_TIMING_DDR52:
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/* Enable DDR mode */
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USDHC_EnableDDRMode(cfg->base, true, 0);
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USDHC_EnableDDRMode(base, true, 0);
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__fallthrough;
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case SDHC_TIMING_SDR12:
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case SDHC_TIMING_SDR25:
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@ -397,10 +411,10 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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break;
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case SDHC_TIMING_HS400:
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#if FSL_FEATURE_USDHC_HAS_HS400_MODE
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USDHC_EnableHS400Mode(cfg->base, true);
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USDHC_EnableDDRMode(cfg->base, true, 0U);
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USDHC_ConfigStrobeDLL(cfg->base, 7U, 4U);
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USDHC_EnableStrobeDLL(cfg->base, true);
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USDHC_EnableHS400Mode(base, true);
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USDHC_EnableDDRMode(base, true, 0U);
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USDHC_ConfigStrobeDLL(base, 7U, 4U);
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USDHC_EnableStrobeDLL(base, true);
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#else
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LOG_ERR("HS400 not supported for this device");
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return -ENOTSUP;
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@ -423,9 +437,9 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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*/
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static int imx_usdhc_transfer(const struct device *dev, struct usdhc_host_transfer *request)
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{
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const struct usdhc_config *cfg = dev->config;
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struct usdhc_data *dev_data = dev->data;
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status_t error;
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USDHC_Type *base = get_base(dev);
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#ifdef CONFIG_IMX_USDHC_DMA_SUPPORT
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usdhc_adma_config_t dma_config = {0};
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@ -443,10 +457,10 @@ static int imx_usdhc_transfer(const struct device *dev, struct usdhc_host_transf
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/* Reset semaphore */
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k_sem_reset(&dev_data->transfer_sem);
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#ifdef CONFIG_IMX_USDHC_DMA_SUPPORT
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error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle, &dma_config,
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error = USDHC_TransferNonBlocking(base, &dev_data->transfer_handle, &dma_config,
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request->transfer);
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#else
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error = USDHC_TransferNonBlocking(cfg->base, &dev_data->transfer_handle, NULL,
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error = USDHC_TransferNonBlocking(base, &dev_data->transfer_handle, NULL,
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request->transfer);
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#endif
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if (error == kStatus_USDHC_ReTuningRequest) {
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@ -504,9 +518,9 @@ static void imx_usdhc_stop_transmission(const struct device *dev)
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*/
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static int imx_usdhc_card_busy(const struct device *dev)
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{
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const struct usdhc_config *cfg = dev->config;
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USDHC_Type *base = get_base(dev);
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return (USDHC_GetPresentStatusFlags(cfg->base) &
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return (USDHC_GetPresentStatusFlags(base) &
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(kUSDHC_Data0LineLevelFlag | kUSDHC_Data1LineLevelFlag | kUSDHC_Data2LineLevelFlag |
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kUSDHC_Data3LineLevelFlag))
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? 0
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@ -518,7 +532,6 @@ static int imx_usdhc_card_busy(const struct device *dev)
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*/
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static int imx_usdhc_execute_tuning(const struct device *dev)
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{
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const struct usdhc_config *cfg = dev->config;
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struct usdhc_data *dev_data = dev->data;
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usdhc_command_t cmd = {0};
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usdhc_data_t data = {0};
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@ -526,6 +539,7 @@ static int imx_usdhc_execute_tuning(const struct device *dev)
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usdhc_transfer_t transfer;
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int ret;
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bool retry_tuning = true;
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USDHC_Type *base = get_base(dev);
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if ((dev_data->host_io.timing == SDHC_TIMING_HS200) ||
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(dev_data->host_io.timing == SDHC_TIMING_HS400)) {
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@ -550,20 +564,20 @@ static int imx_usdhc_execute_tuning(const struct device *dev)
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transfer.data = &data;
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/* Reset tuning circuit */
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USDHC_Reset(cfg->base, kUSDHC_ResetTuning, 100U);
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USDHC_Reset(base, kUSDHC_ResetTuning, 100U);
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/* Disable standard tuning */
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USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START,
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IMX_USDHC_TUNING_STEP, false);
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USDHC_ForceClockOn(cfg->base, true);
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USDHC_EnableStandardTuning(base, IMX_USDHC_STANDARD_TUNING_START, IMX_USDHC_TUNING_STEP,
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false);
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USDHC_ForceClockOn(base, true);
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/*
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* Tuning fail found on some SOCs is caused by the different of delay
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* cell, so we need to increase the tuning counter to cover the
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* adjustable tuning window
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*/
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USDHC_SetStandardTuningCounter(cfg->base, IMX_USDHC_STANDARD_TUNING_COUNTER);
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USDHC_SetStandardTuningCounter(base, IMX_USDHC_STANDARD_TUNING_COUNTER);
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/* Reenable standard tuning */
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USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START,
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IMX_USDHC_TUNING_STEP, true);
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USDHC_EnableStandardTuning(base, IMX_USDHC_STANDARD_TUNING_START, IMX_USDHC_TUNING_STEP,
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true);
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request.command_timeout = K_MSEC(IMX_USDHC_DEFAULT_TIMEOUT);
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request.data_timeout = K_MSEC(IMX_USDHC_DEFAULT_TIMEOUT);
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@ -578,29 +592,29 @@ static int imx_usdhc_execute_tuning(const struct device *dev)
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k_busy_wait(1000);
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/* Wait for execute tuning bit to clear */
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if (USDHC_GetExecuteStdTuningStatus(cfg->base) != 0) {
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if (USDHC_GetExecuteStdTuningStatus(base) != 0) {
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continue;
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}
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/* If tuning had error, retry tuning */
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if ((USDHC_CheckTuningError(cfg->base) != 0U) && retry_tuning) {
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if ((USDHC_CheckTuningError(base) != 0U) && retry_tuning) {
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retry_tuning = false;
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/* Enable standard tuning */
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USDHC_EnableStandardTuning(cfg->base, IMX_USDHC_STANDARD_TUNING_START,
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USDHC_EnableStandardTuning(base, IMX_USDHC_STANDARD_TUNING_START,
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IMX_USDHC_TUNING_STEP, true);
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USDHC_SetTuningDelay(cfg->base, IMX_USDHC_STANDARD_TUNING_START, 0U, 0U);
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USDHC_SetTuningDelay(base, IMX_USDHC_STANDARD_TUNING_START, 0U, 0U);
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} else {
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break;
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}
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}
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/* Check tuning result */
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if (USDHC_CheckStdTuningResult(cfg->base) == 0) {
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if (USDHC_CheckStdTuningResult(base) == 0) {
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return -EIO;
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}
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USDHC_ForceClockOn(cfg->base, false);
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USDHC_ForceClockOn(base, false);
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/* Enable auto tuning */
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USDHC_EnableAutoTuning(cfg->base, true);
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USDHC_EnableAutoTuning(base, true);
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return 0;
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}
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@ -610,7 +624,6 @@ static int imx_usdhc_execute_tuning(const struct device *dev)
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static int imx_usdhc_request(const struct device *dev, struct sdhc_command *cmd,
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struct sdhc_data *data)
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{
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const struct usdhc_config *cfg = dev->config;
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struct usdhc_data *dev_data = dev->data;
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usdhc_command_t host_cmd = {0};
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usdhc_data_t host_data = {0};
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@ -619,9 +632,10 @@ static int imx_usdhc_request(const struct device *dev, struct sdhc_command *cmd,
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int busy_timeout = IMX_USDHC_DEFAULT_TIMEOUT;
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int ret = 0;
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int retries = (int)cmd->retries;
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USDHC_Type *base = get_base(dev);
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if (cmd->opcode == SD_GO_IDLE_STATE) {
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USDHC_SetCardActive(cfg->base, 0xFFFF);
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USDHC_SetCardActive(base, 0xFFFF);
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}
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host_cmd.index = cmd->opcode;
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@ -714,12 +728,10 @@ static int imx_usdhc_request(const struct device *dev, struct sdhc_command *cmd,
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* the USDHC driver expects data to be present in the
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* current transmission, but CMD12 does not contain data
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*/
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USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CommandFlag |
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kUSDHC_DataFlag |
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kUSDHC_DataDMAFlag);
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USDHC_ClearInterruptStatusFlags(cfg->base, kUSDHC_CommandFlag |
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kUSDHC_DataFlag |
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kUSDHC_DataDMAFlag);
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USDHC_DisableInterruptSignal(base, kUSDHC_CommandFlag | kUSDHC_DataFlag |
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kUSDHC_DataDMAFlag);
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USDHC_ClearInterruptStatusFlags(base, kUSDHC_CommandFlag | kUSDHC_DataFlag |
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kUSDHC_DataDMAFlag);
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/* Stop transmission with CMD12 in case of data error */
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imx_usdhc_stop_transmission(dev);
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/* Wait for card to go idle */
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@ -779,6 +791,7 @@ static int imx_usdhc_get_card_present(const struct device *dev)
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{
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const struct usdhc_config *cfg = dev->config;
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struct usdhc_data *data = dev->data;
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USDHC_Type *base = get_base(dev);
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if (cfg->detect_dat3) {
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/*
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@ -788,20 +801,20 @@ static int imx_usdhc_get_card_present(const struct device *dev)
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if (!data->card_present) {
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/* Detect card presence with DAT3 line pull */
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imx_usdhc_dat3_pull(cfg, false);
|
||||
USDHC_CardDetectByData3(cfg->base, true);
|
||||
USDHC_CardDetectByData3(base, true);
|
||||
/* Delay to ensure host has time to detect card */
|
||||
k_busy_wait(1000);
|
||||
data->card_present = USDHC_DetectCardInsert(cfg->base);
|
||||
data->card_present = USDHC_DetectCardInsert(base);
|
||||
/* Clear card detection and pull */
|
||||
imx_usdhc_dat3_pull(cfg, true);
|
||||
USDHC_CardDetectByData3(cfg->base, false);
|
||||
USDHC_CardDetectByData3(base, false);
|
||||
}
|
||||
} else if (cfg->detect_cd) {
|
||||
/*
|
||||
* Detect the card via the USDHC_CD signal internal to
|
||||
* the peripheral
|
||||
*/
|
||||
data->card_present = USDHC_DetectCardInsert(cfg->base);
|
||||
data->card_present = USDHC_DetectCardInsert(base);
|
||||
} else if (cfg->detect_gpio.port) {
|
||||
data->card_present = gpio_pin_get_dt(&cfg->detect_gpio) > 0;
|
||||
} else {
|
||||
|
|
@ -831,6 +844,7 @@ static int imx_usdhc_enable_interrupt(const struct device *dev, sdhc_interrupt_c
|
|||
{
|
||||
const struct usdhc_config *cfg = dev->config;
|
||||
struct usdhc_data *data = dev->data;
|
||||
USDHC_Type *base = get_base(dev);
|
||||
int ret;
|
||||
|
||||
/* Record SDIO callback parameters */
|
||||
|
|
@ -838,24 +852,24 @@ static int imx_usdhc_enable_interrupt(const struct device *dev, sdhc_interrupt_c
|
|||
data->sdhc_cb_user_data = user_data;
|
||||
|
||||
/* Disable interrupts, then enable what the user requested */
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardInterruptFlag);
|
||||
if (cfg->detect_gpio.port) {
|
||||
ret = gpio_pin_interrupt_configure_dt(&cfg->detect_gpio, GPIO_INT_DISABLE);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardRemovalFlag);
|
||||
}
|
||||
|
||||
if (sources & SDHC_INT_SDIO) {
|
||||
/* Enable SDIO card interrupt */
|
||||
USDHC_EnableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_EnableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_EnableInterruptStatus(base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_EnableInterruptSignal(base, kUSDHC_CardInterruptFlag);
|
||||
}
|
||||
if (sources & SDHC_INT_INSERTED) {
|
||||
if (cfg->detect_gpio.port) {
|
||||
|
|
@ -867,8 +881,8 @@ static int imx_usdhc_enable_interrupt(const struct device *dev, sdhc_interrupt_c
|
|||
}
|
||||
} else {
|
||||
/* Enable card insertion interrupt */
|
||||
USDHC_EnableInterruptStatus(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_EnableInterruptSignal(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_EnableInterruptStatus(base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_EnableInterruptSignal(base, kUSDHC_CardInsertionFlag);
|
||||
}
|
||||
}
|
||||
if (sources & SDHC_INT_REMOVED) {
|
||||
|
|
@ -881,8 +895,8 @@ static int imx_usdhc_enable_interrupt(const struct device *dev, sdhc_interrupt_c
|
|||
}
|
||||
} else {
|
||||
/* Enable card removal interrupt */
|
||||
USDHC_EnableInterruptStatus(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_EnableInterruptSignal(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_EnableInterruptStatus(base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_EnableInterruptSignal(base, kUSDHC_CardRemovalFlag);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -893,12 +907,13 @@ static int imx_usdhc_disable_interrupt(const struct device *dev, int sources)
|
|||
{
|
||||
const struct usdhc_config *cfg = dev->config;
|
||||
struct usdhc_data *data = dev->data;
|
||||
USDHC_Type *base = get_base(dev);
|
||||
int ret;
|
||||
|
||||
if (sources & SDHC_INT_SDIO) {
|
||||
/* Disable SDIO card interrupt */
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardInterruptFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardInterruptFlag);
|
||||
}
|
||||
if (sources & SDHC_INT_INSERTED) {
|
||||
if (cfg->detect_gpio.port) {
|
||||
|
|
@ -908,8 +923,8 @@ static int imx_usdhc_disable_interrupt(const struct device *dev, int sources)
|
|||
}
|
||||
} else {
|
||||
/* Disable card insertion interrupt */
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardInsertionFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardInsertionFlag);
|
||||
}
|
||||
}
|
||||
if (sources & SDHC_INT_REMOVED) {
|
||||
|
|
@ -920,13 +935,13 @@ static int imx_usdhc_disable_interrupt(const struct device *dev, int sources)
|
|||
}
|
||||
} else {
|
||||
/* Disable card removal interrupt */
|
||||
USDHC_DisableInterruptStatus(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptSignal(cfg->base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptStatus(base, kUSDHC_CardRemovalFlag);
|
||||
USDHC_DisableInterruptSignal(base, kUSDHC_CardRemovalFlag);
|
||||
}
|
||||
}
|
||||
|
||||
/* If all interrupt flags are disabled, remove callback */
|
||||
if ((USDHC_GetEnabledInterruptStatusFlags(cfg->base) &
|
||||
if ((USDHC_GetEnabledInterruptStatusFlags(base) &
|
||||
(kUSDHC_CardInterruptFlag | kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag)) == 0) {
|
||||
data->sdhc_cb = NULL;
|
||||
data->sdhc_cb_user_data = NULL;
|
||||
|
|
@ -937,10 +952,10 @@ static int imx_usdhc_disable_interrupt(const struct device *dev, int sources)
|
|||
|
||||
static int imx_usdhc_isr(const struct device *dev)
|
||||
{
|
||||
const struct usdhc_config *cfg = dev->config;
|
||||
USDHC_Type *base = get_base(dev);
|
||||
struct usdhc_data *data = dev->data;
|
||||
|
||||
USDHC_TransferHandleIRQ(cfg->base, &data->transfer_handle);
|
||||
USDHC_TransferHandleIRQ(base, &data->transfer_handle);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -952,6 +967,7 @@ static int imx_usdhc_init(const struct device *dev)
|
|||
const struct usdhc_config *cfg = dev->config;
|
||||
struct usdhc_data *data = dev->data;
|
||||
usdhc_config_t host_config = {0};
|
||||
USDHC_Type *base;
|
||||
int ret;
|
||||
const usdhc_transfer_callback_t callbacks = {
|
||||
.TransferComplete = transfer_complete_cb,
|
||||
|
|
@ -960,6 +976,8 @@ static int imx_usdhc_init(const struct device *dev)
|
|||
.CardRemoved = card_removed_cb,
|
||||
};
|
||||
|
||||
DEVICE_MMIO_NAMED_MAP(dev, usdhc_mmio, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
|
||||
|
||||
if (!device_is_ready(cfg->clock_dev)) {
|
||||
LOG_ERR("clock control device not ready");
|
||||
return -ENODEV;
|
||||
|
|
@ -969,14 +987,15 @@ static int imx_usdhc_init(const struct device *dev)
|
|||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
USDHC_TransferCreateHandle(cfg->base, &data->transfer_handle, &callbacks, (void *)dev);
|
||||
base = get_base(dev);
|
||||
USDHC_TransferCreateHandle(base, &data->transfer_handle, &callbacks, (void *)dev);
|
||||
cfg->irq_config_func(dev);
|
||||
|
||||
host_config.dataTimeout = cfg->data_timeout;
|
||||
host_config.endianMode = kUSDHC_EndianModeLittle;
|
||||
host_config.readWatermarkLevel = cfg->read_watermark;
|
||||
host_config.writeWatermarkLevel = cfg->write_watermark;
|
||||
USDHC_Init(cfg->base, &host_config);
|
||||
USDHC_Init(base, &host_config);
|
||||
/* Read host controller properties */
|
||||
imx_usdhc_init_host_props(dev);
|
||||
/* Set power GPIO low, so card starts powered off */
|
||||
|
|
@ -1056,7 +1075,7 @@ static DEVICE_API(sdhc, usdhc_api) = {
|
|||
PINCTRL_DT_INST_DEFINE(n); \
|
||||
\
|
||||
static const struct usdhc_config usdhc_##n##_config = { \
|
||||
.base = (USDHC_Type *)DT_INST_REG_ADDR(n), \
|
||||
DEVICE_MMIO_NAMED_ROM_INIT(usdhc_mmio, DT_DRV_INST(n)), \
|
||||
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
|
||||
.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
|
||||
.nusdhc = n, \
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue