soc: atmel: move init code from SYS_INIT to hooks

Replace SYS_INIT with SoC hooks and adapt SoC init code

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2024-09-10 09:42:29 -04:00 committed by Henrik Brix Andersen
commit 51c771ecb2
6 changed files with 10 additions and 29 deletions

View file

@ -17,3 +17,4 @@ config SOC_SERIES_SAME70
select HAS_SWO
select XIP
select HAS_POWEROFF
select SOC_EARLY_INIT_HOOK

View file

@ -135,23 +135,18 @@ void soc_reset_hook(void)
clock_init();
}
extern void atmel_same70_config(void);
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_same70_init(void)
void soc_early_init_hook(void)
{
/* Check that the CHIP CIDR matches the HAL one */
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
}
return 0;
atmel_same70_config();
}
SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0);

View file

@ -18,10 +18,8 @@
*
* This should be run early during the boot process but after basic hardware
* initialization is done.
*
* @return 0
*/
static int atmel_same70_config(void)
void atmel_same70_config(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
/* Disable ERASE function on PB12 pin, this is controlled
@ -59,7 +57,4 @@ static int atmel_same70_config(void)
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
}
return 0;
}
SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1);

View file

@ -17,3 +17,4 @@ config SOC_SERIES_SAMV71
select HAS_SWO
select XIP
select HAS_POWEROFF
select SOC_EARLY_INIT_HOOK

View file

@ -132,23 +132,18 @@ void soc_reset_hook(void)
clock_init();
}
extern void atmel_samv71_config(void);
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_samv71_init(void)
void soc_early_init_hook(void)
{
/* Check that the CHIP CIDR matches the HAL one */
if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
}
return 0;
atmel_samv71_config();
}
SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0);

View file

@ -18,10 +18,8 @@
*
* This should be run early during the boot process but after basic hardware
* initialization is done.
*
* @return 0
*/
static int atmel_samv71_config(void)
void atmel_samv71_config(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
/* Disable ERASE function on PB12 pin, this is controlled
@ -59,8 +57,4 @@ static int atmel_samv71_config(void)
/* Disable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
}
return 0;
}
SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1);