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linker: Make alignment size for sw_isr_table configurable

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sw_isr_table has two entries, an argument and an ISR function.  The
comment on struct _isr_table_entry in include/sw_isr_table.h says that
"This allows a table entry to be loaded [...] with one ldmia
instruction, on ARM [...]".  Some arch, e.g. SPARC, also has a double
word load instruction, "ldd", but the instruct must have address align
to double word or 8 bytes.

This commit makes the table alignment configurable.  It allows each
architecture to specify it, if needed.  The default value is 0 for no
alignment.

Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
This commit is contained in:
Yasushi SHOJI 2019-06-20 18:28:37 +09:00 • committed by Andrew Boie
commit 51bc0a065c
3 changed files with 22 additions and 0 deletions
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6
include/linker/common-ram.ld
View file

@ -8,6 +8,12 @@
#if defined(CONFIG_GEN_ISR_TABLES) && defined(CONFIG_DYNAMIC_INTERRUPTS)
SECTION_DATA_PROLOGUE(sw_isr_table,,)
{
/*
* Some arch requires an entry to be aligned to arch
* specific boundary for using double word load
* instruction. See include/sw_isr_table.h.
*/
. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);
*(SW_ISR_TABLE)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
#endif

6
include/linker/common-rom.ld
View file

@ -3,6 +3,12 @@
#if defined(CONFIG_GEN_ISR_TABLES) && !defined(CONFIG_DYNAMIC_INTERRUPTS)
SECTION_PROLOGUE(sw_isr_table,,)
{
/*
* Some arch requires an entry to be aligned to arch
* specific boundary for using double word load
* instruction. See include/sw_isr_table.h.
*/
. = ALIGN(CONFIG_ARCH_SW_ISR_TABLE_ALIGN);
*(SW_ISR_TABLE)
} GROUP_LINK_IN(ROMABLE_REGION)
#endif