driver: adc: microchip: Merged MEC172x and MEC15xx version drivers.
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and MEC15xx SOC. ADC smapling clock configuration updated using DTS. Signed-off-by: Manimaran A <manimaran.a@microchip.com>
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51b1c5b9d6
4 changed files with 58 additions and 7 deletions
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@ -12,7 +12,9 @@
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LOG_MODULE_REGISTER(adc_mchp_xec);
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#include <zephyr/drivers/adc.h>
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#ifdef CONFIG_SOC_SERIES_MEC172X
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#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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#endif
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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@ -302,6 +304,39 @@ static void xec_adc_get_sample(const struct device *dev)
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regs->status_reg = ch_status;
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}
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#ifdef CONFIG_SOC_SERIES_MEC172X
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static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
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{
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mchp_xec_ecia_girq_src_clr(girq_idx, girq_posn);
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}
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static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
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{
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mchp_xec_ecia_girq_src_en(girq_idx, girq_posn);
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}
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static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
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{
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mchp_xec_ecia_girq_src_dis(girq_idx, girq_posn);
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}
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#else
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static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
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{
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MCHP_GIRQ_SRC(girq_idx) = BIT(girq_posn);
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}
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static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
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{
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MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn);
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}
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static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
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{
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MCHP_GIRQ_ENCLR(girq_idx) = MCHP_KBC_IBF_GIRQ;
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}
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#endif
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static void adc_xec_single_isr(const struct device *dev)
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{
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const struct adc_xec_config *const cfg = dev->config;
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@ -316,7 +351,7 @@ static void adc_xec_single_isr(const struct device *dev)
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regs->control_reg = ctrl;
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/* Also clear GIRQ source status bit */
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mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
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adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
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xec_adc_get_sample(dev);
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@ -329,6 +364,7 @@ static void adc_xec_single_isr(const struct device *dev)
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LOG_DBG("ADC ISR triggered.");
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}
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#ifdef CONFIG_PM_DEVICE
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static int adc_xec_pm_action(const struct device *dev, enum pm_device_action action)
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{
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@ -370,6 +406,11 @@ struct adc_driver_api adc_xec_api = {
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.ref_internal = XEC_ADC_VREF_ANALOG,
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};
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/* ADC Config Register */
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#define XEC_ADC_CFG_CLK_VAL(clk_time) ( \
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(clk_time << MCHP_ADC_CFG_CLK_LO_TIME_POS) | \
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(clk_time << MCHP_ADC_CFG_CLK_HI_TIME_POS))
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static int adc_xec_init(const struct device *dev)
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{
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const struct adc_xec_config *const cfg = dev->config;
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@ -385,16 +426,18 @@ static int adc_xec_init(const struct device *dev)
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return ret;
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}
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regs->config_reg = XEC_ADC_CFG_CLK_VAL(DT_INST_PROP(0, clktime));
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regs->control_reg = XEC_ADC_CTRL_ACTIVATE
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| XEC_ADC_CTRL_POWER_SAVER_DIS
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| XEC_ADC_CTRL_SINGLE_DONE_STATUS
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| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
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mchp_xec_ecia_girq_src_dis(cfg->girq_single, cfg->girq_single_pos);
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mchp_xec_ecia_girq_src_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
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mchp_xec_ecia_girq_src_clr(cfg->girq_single, cfg->girq_single_pos);
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mchp_xec_ecia_girq_src_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
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mchp_xec_ecia_girq_src_en(cfg->girq_single, cfg->girq_single_pos);
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adc_xec_girq_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
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adc_xec_girq_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
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adc_xec_girq_dis(cfg->girq_single, cfg->girq_single_pos);
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adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
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adc_xec_girq_en(cfg->girq_single, cfg->girq_single_pos);
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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@ -416,9 +416,11 @@
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#pwm-cells = <3>;
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};
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adc0: adc@40007c00 {
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compatible = "microchip,xec-adc";
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compatible = "microchip,xec-adc-v2";
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reg = <0x40007c00 0x90>;
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interrupts = <78 0>, <79 0>;
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girqs = <17 8>, <17 9>;
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pcrs = <3 3>;
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status = "disabled";
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#io-channel-cells = <1>;
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clktime = <32>;
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@ -695,6 +695,7 @@
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pcrs = <3 3>;
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status = "disabled";
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#io-channel-cells = <1>;
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clktime = <32>;
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};
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kscan0: kscan@40009c00 {
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compatible = "microchip,xec-kscan";
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@ -28,6 +28,11 @@ properties:
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required: true
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description: ADC PCR register index and bit position
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clktime:
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type: int
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required: true
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description: ADC clock high & low time count value <1:255>
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pinctrl-0:
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required: true
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