From 5183e5e6067816a89965129093f040281db6965d Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 5 Aug 2021 12:57:20 -0700 Subject: [PATCH] soc/intel_adsp: Fix region cacheability for MP cores On MP cores that don't come through the core entry point (e.g. TGL/v2.5) we reach C code with hardware defaults for the RPO/TLB settings. Set these up correctly on entry. Signed-off-by: Andy Ross --- soc/xtensa/intel_adsp/common/soc_mp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 2580a545ec0..24bf80c65b9 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -122,6 +122,23 @@ void z_mp_entry(void) volatile int ie; uint32_t idc_reg; + /* Correct the Region Protection Option cachability settings. + * The hardware defaults (everything accessible and uncached) + * don't match the design intent. Registers in the first + * region are RW but uncached, as is the RAM mapped in the + * fifth. The same RAM in the sixth is mapped cached. Note + * that there's actually a HAL call to do this by emulating + * the older cacheattr feature, but it generates significantly + * more code. + */ + const uint32_t attribs[] = { 2, 15, 15, 15, 2, 4, 15, 15 }; + + for (int region = 0; region < 8; region++) { + uint32_t addr = 0x20000000 * region; + + __asm__ volatile("wdtlb %0, %1" :: "r"(attribs[region]), "r"(addr)); + } + /* We don't know what the boot ROM might have touched and we * don't care. Make sure it's not in our local cache to be * flushed accidentally later.