tests/drivers/clock_control: stm32: Factorize wl/wb clear clocks overlay

Since they don't have impact on sysclock src configuration,
remove LSI/E clocks from clear clocks overlays.
This enables the possibility to factorize wl and wb clear clocks overlays
and brings some use cases factorizations as well.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>

tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/clear_clocks.overlay

@@ -20,14 +20,6 @@
 	/delete-property/ hsi-div;
 };
 
-&clk_lse {
-	status = "disabled";
-};
-
-&clk_lsi {
-	status = "disabled";
-};
-
 &pll {
 	/delete-property/ div-m;
 	/delete-property/ mul-n;

tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_clear_clocks.overlay

@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2022 STMicroelectronics
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * Warning: This overlay clears clocks back to a state equivalent to what could
- * be found in stm32wb.dtsi
- */
-
-&clk_hse {
-	status = "disabled";
-	/delete-property/ hse-bypass;
-	/delete-property/ clock-frequency;
-};
-
-&clk_hsi {
-	status = "disabled";
-	/delete-property/ hsi-div;
-};
-
-&clk_lse {
-	status = "disabled";
-};
-
-&clk_lsi1 {
-	status = "disabled";
-};
-
-&clk_lsi2 {
-	status = "disabled";
-};
-
-&clk_msi {
-	status = "disabled";
-	/delete-property/ msi-range;
-};
-
-&pll {
-	/delete-property/ div-m;
-	/delete-property/ mul-n;
-	/delete-property/ div-p;
-	/delete-property/ div-q;
-	/delete-property/ div-r;
-	/delete-property/ clocks;
-	status = "disabled";
-};
-
-&rcc {
-	/delete-property/ clocks;
-	/delete-property/ clock-frequency;
-};

tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wb_pll_48_msi_4.overlay

@@ -6,7 +6,7 @@
 
 /*
  * Warning: This overlay performs configuration from clean sheet.
- * It is assumed that it is applied after wb_clear_clocks.overlay file.
+ * It is assumed that it is applied after wx_clear_clocks.overlay file.
  * It applies to the stm32wb where the msi is 4MHz
  */
 

tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wx_clear_clocks.overlay

@@ -21,14 +21,6 @@
 	/delete-property/ hsi-div;
 };
 
-&clk_lse {
-	status = "disabled";
-};
-
-&clk_lsi {
-	status = "disabled";
-};
-
 &clk_msi {
 	status = "disabled";
 	/delete-property/ msi-range;

tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml

@@ -56,10 +56,10 @@ tests:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msi_range6.overlay"
     platform_allow: nucleo_l152re nucleo_l073rz
   drivers.stm32_clock_configuration.common.wl.sysclksrc_pll_48_hsi_16:
-    extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/pll_48_hsi_16.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/pll_48_hsi_16.overlay"
     platform_allow: nucleo_wl55jc
   drivers.stm32_clock_configuration.common.wl.sysclksrc_pll_48_hse_32:
-    extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
     platform_allow: nucleo_wl55jc
   drivers.stm32_clock_configuration.common.wl.sysclksrc_hse_32:
     extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/wl_32_hse.overlay"
@@ -70,23 +70,20 @@ tests:
   drivers.stm32_clock_configuration.common.l4_l5.sysclksrc_msi_48:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/msi_range11.overlay"
     platform_allow: disco_l475_iot1 nucleo_l4r5zi stm32l562e_dk
-  drivers.stm32_clock_configuration.common.wb.sysclksrc_msi_48:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/msi_range11.overlay"
-    platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.wb.sysclksrc_hsi_16:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/hsi_16.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/hsi_16.overlay"
     platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.wb.sysclksrc_hse_32:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/hse_32.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/hse_32.overlay"
     platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.wb.sysclksrc_pll_48_hsi_16:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_hsi_16.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/wb_pll_48_hsi_16.overlay"
     platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.wb.sysclksrc_pll_64_hse_32:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_64_hse_32.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/wb_pll_64_hse_32.overlay"
     platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.wb.sysclksrc_pll_48_msi_4:
-    extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/wx_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
     platform_allow: nucleo_wb55rg
   drivers.stm32_clock_configuration.common.l4_l5.sysclksrc_pll_48_msi_4:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_48_msi_4.overlay"