drivers/flash: stm32wb: Add HSEM
Add HSEM for Flash access since shared between 2 cores. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
parent
2566981294
commit
51033a5814
2 changed files with 22 additions and 0 deletions
|
@ -34,6 +34,8 @@
|
||||||
#define STM32_FLASH_TIMEOUT (K_MSEC(25))
|
#define STM32_FLASH_TIMEOUT (K_MSEC(25))
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#define CFG_HW_FLASH_SEMID 2
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This is named flash_stm32_sem_take instead of flash_stm32_lock (and
|
* This is named flash_stm32_sem_take instead of flash_stm32_lock (and
|
||||||
* similarly for flash_stm32_sem_give) to avoid confusion with locking
|
* similarly for flash_stm32_sem_give) to avoid confusion with locking
|
||||||
|
@ -41,12 +43,24 @@
|
||||||
*/
|
*/
|
||||||
static inline void flash_stm32_sem_take(struct device *dev)
|
static inline void flash_stm32_sem_take(struct device *dev)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_SERIES_STM32WBX
|
||||||
|
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID))
|
||||||
|
;
|
||||||
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */
|
||||||
|
|
||||||
k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
|
k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void flash_stm32_sem_give(struct device *dev)
|
static inline void flash_stm32_sem_give(struct device *dev)
|
||||||
{
|
{
|
||||||
|
|
||||||
k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
|
k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_SERIES_STM32WBX
|
||||||
|
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
|
||||||
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
|
#if !defined(CONFIG_SOC_SERIES_STM32WBX)
|
||||||
|
@ -294,6 +308,10 @@ static int stm32_flash_init(struct device *dev)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_SERIES_STM32WBX
|
||||||
|
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
|
||||||
|
#endif /* CONFIG_SOC_SERIES_STM32WBX */
|
||||||
|
|
||||||
k_sem_init(&p->sem, 1, 1);
|
k_sem_init(&p->sem, 1, 1);
|
||||||
|
|
||||||
return flash_stm32_write_protection(dev, false);
|
return flash_stm32_write_protection(dev, false);
|
||||||
|
|
|
@ -43,6 +43,10 @@
|
||||||
#include <stm32wbxx_ll_system.h>
|
#include <stm32wbxx_ll_system.h>
|
||||||
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
|
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
|
||||||
|
|
||||||
|
#ifdef CONFIG_FLASH
|
||||||
|
#include <stm32wbxx_ll_hsem.h>
|
||||||
|
#endif /* CONFIG_FLASH */
|
||||||
|
|
||||||
#endif /* !_ASMLANGUAGE */
|
#endif /* !_ASMLANGUAGE */
|
||||||
|
|
||||||
#endif /* _STM32WBX_SOC_H_ */
|
#endif /* _STM32WBX_SOC_H_ */
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue