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arch: arm: aarch32: Fix whitespaces in cpu_idle.S

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This commit fixes whitespaces in cpu_idle.S.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-03-18 09:58:10 +09:00 • committed by Ioannis Glaropoulos
commit 50e4f2a671
1 changed files with 32 additions and 32 deletions
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64
arch/arm/core/aarch32/cpu_idle.S
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@ -20,12 +20,12 @@ GTEXT(arch_cpu_idle)
GTEXT(arch_cpu_atomic_idle) GTEXT(arch_cpu_atomic_idle)
#if defined(CONFIG_CPU_CORTEX_M) #if defined(CONFIG_CPU_CORTEX_M)
#define _SCB_SCR 0xE000ED10 #define _SCB_SCR 0xE000ED10
#define _SCB_SCR_SEVONPEND (1 << 4) #define _SCB_SCR_SEVONPEND (1 << 4)
#define _SCB_SCR_SLEEPDEEP (1 << 2) #define _SCB_SCR_SLEEPDEEP (1 << 2)
#define _SCB_SCR_SLEEPONEXIT (1 << 1) #define _SCB_SCR_SLEEPONEXIT (1 << 1)
#define _SCR_INIT_BITS _SCB_SCR_SEVONPEND #define _SCR_INIT_BITS _SCB_SCR_SEVONPEND
#endif #endif
/** /**
@ -44,48 +44,48 @@ GTEXT(arch_cpu_atomic_idle)
SECTION_FUNC(TEXT, z_arm_cpu_idle_init) SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
#if defined(CONFIG_CPU_CORTEX_M) #if defined(CONFIG_CPU_CORTEX_M)
ldr r1, =_SCB_SCR ldr r1, =_SCB_SCR
movs.n r2, #_SCR_INIT_BITS movs.n r2, #_SCR_INIT_BITS
str r2, [r1] str r2, [r1]
#endif #endif
bx lr bx lr
SECTION_FUNC(TEXT, arch_cpu_idle) SECTION_FUNC(TEXT, arch_cpu_idle)
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
push {r0, lr} push {r0, lr}
bl sys_trace_idle bl sys_trace_idle
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r1} pop {r0, r1}
mov lr, r1 mov lr, r1
#else #else
pop {r0, lr} pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */ #endif /* CONFIG_TRACING */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \ #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
|| defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_R)
cpsie i cpsie i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* clear BASEPRI so wfi is awakened by incoming interrupts */ /* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0 eors.n r0, r0
msr BASEPRI, r0 msr BASEPRI, r0
#else #else
#error Unknown ARM architecture #error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
wfi wfi
bx lr bx lr
SECTION_FUNC(TEXT, arch_cpu_atomic_idle) SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
#ifdef CONFIG_TRACING #ifdef CONFIG_TRACING
push {r0, lr} push {r0, lr}
bl sys_trace_idle bl sys_trace_idle
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r1} pop {r0, r1}
mov lr, r1 mov lr, r1
#else #else
pop {r0, lr} pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_TRACING */ #endif /* CONFIG_TRACING */
@ -93,7 +93,7 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
* Lock PRIMASK while sleeping: wfe will still get interrupted by * Lock PRIMASK while sleeping: wfe will still get interrupted by
* incoming interrupts but the CPU will not service them right away. * incoming interrupts but the CPU will not service them right away.
*/ */
cpsid i cpsid i
/* /*
* No need to set SEVONPEND, it's set once in z_CpuIdleInit() and never * No need to set SEVONPEND, it's set once in z_CpuIdleInit() and never
@ -107,23 +107,23 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
/* No BASEPRI, call wfe directly (SEVONPEND set in z_CpuIdleInit()) */ /* No BASEPRI, call wfe directly (SEVONPEND set in z_CpuIdleInit()) */
wfe wfe
cmp r0, #0 cmp r0, #0
bne _irq_disabled bne _irq_disabled
cpsie i cpsie i
_irq_disabled: _irq_disabled:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* r1: zero, for setting BASEPRI (needs a register) */ /* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1 eors.n r1, r1
/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */ /* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
msr BASEPRI, r1 msr BASEPRI, r1
wfe wfe
msr BASEPRI, r0 msr BASEPRI, r0
cpsie i cpsie i
#else #else
#error Unknown ARM architecture #error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
bx lr bx lr