From 5098aaa2d1ce869bef8c080a025d4864eb46739a Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Thu, 14 Apr 2022 14:16:39 +0200 Subject: [PATCH] hwinfo: hwinfo_litex: Make compatible with both 8 and 32-bit CSRs LiteX CSRs can only be accessed on addresses aligned to 4 bytes. That's why in 32-bit CSRs case there is bit shifting needed. Signed-off-by: Michal Sieron --- drivers/hwinfo/hwinfo_litex.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/hwinfo/hwinfo_litex.c b/drivers/hwinfo/hwinfo_litex.c index 5cc73785be6..dc3351bbf36 100644 --- a/drivers/hwinfo/hwinfo_litex.c +++ b/drivers/hwinfo/hwinfo_litex.c @@ -14,14 +14,19 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { - uint32_t volatile *ptr = (uint32_t volatile *)(DT_INST_REG_ADDR(0)); - ssize_t end = MIN(length, (DT_INST_REG_SIZE(0) / sizeof(uint32_t))); - + uint32_t addr = DT_INST_REG_ADDR(0); + ssize_t end = MIN(length, DT_INST_REG_ADDR(0) / 4 * + CONFIG_LITEX_CSR_DATA_WIDTH / 8); for (int i = 0; i < end; i++) { - /* In LiteX even though registers are 32-bit wide, each one - contains meaningful data only in the lowest 8 bits */ - buffer[i] = (uint8_t)(ptr[i] & 0xff); +#if CONFIG_LITEX_CSR_DATA_WIDTH == 8 + buffer[i] = litex_read8(addr); + addr += 4; +#elif CONFIG_LITEX_CSR_DATA_WIDTH == 32 + buffer[i] = (uint8_t)(litex_read32(addr) >> (addr % 4 * 8)); + addr += 1; +#else +#error Unsupported CSR data width +#endif } - return end; }