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driver: clock_controller: return values of clock_control apis directly.

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return values of clock_control_on()/clock_control_get_rate() directly in
case overwriting error codes.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This commit is contained in:
Mulin Chao 2020-10-14 11:47:20 +08:00 • committed by Anas Nashif
commit 507f31472c
7 changed files with 57 additions and 35 deletions
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20
drivers/adc/adc_npcx.c
View file

@ -335,22 +335,24 @@ static int adc_npcx_init(const struct device *dev)
struct adc_reg *const inst = HAL_INSTANCE(dev);
const struct device *const clk_dev =
device_get_binding(NPCX_CLK_CTRL_NAME);
int prescaler = 0;
int prescaler = 0, ret;
/* Save ADC device in data */
data->adc_dev = dev;
/* Turn on device clock first and get source clock freq. */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *)&config->clk_cfg) != 0) {
LOG_ERR("Turn on ADC clock fail.");
return -EIO;
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on ADC clock fail %d", ret);
return ret;
}
if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg, &data->input_clk) != 0) {
LOG_ERR("Get ADC clock rate error.");
return -EIO;
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg, &data->input_clk);
if (ret < 0) {
LOG_ERR("Get ADC clock rate error %d", ret);
return ret;
}
/* Configure the ADC clock */

6
drivers/clock_control/clock_control_npcx.c
View file

@ -39,6 +39,9 @@ static inline int npcx_clock_control_on(const struct device *dev,
struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT || clk_cfg->bit >= 8)
return -EINVAL;
/* Clear related PD (Power-Down) bit of module to turn on clock */
NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
return 0;
@ -51,6 +54,9 @@ static inline int npcx_clock_control_off(const struct device *dev,
struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
if (clk_cfg->ctrl >= NPCX_PWDWN_CTL_COUNT || clk_cfg->bit >= 8)
return -EINVAL;
/* Set related PD (Power-Down) bit of module to turn off clock */
NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);
return 0;

10
drivers/espi/espi_npcx.c
View file

@ -827,12 +827,14 @@ static int espi_npcx_init(const struct device *dev)
struct espi_npcx_data *const data = DRV_DATA(dev);
struct espi_reg *const inst = HAL_INSTANCE(dev);
const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME);
int i;
int i, ret;
/* Turn on eSPI device clock first */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg) != 0) {
return -EIO;
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on eSPI clock fail %d", ret);
return ret;
}
/* Enable events which share the same espi bus interrupt */

13
drivers/espi/host_subs_npcx.c
View file

@ -757,11 +757,14 @@ int npcx_host_init_subs_core_domain(const struct device *host_bus_dev,
host_sub_data.host_bus_dev = host_bus_dev;
/* Turn on all host necessary sub-module clocks first */
for (i = 0; i < host_sub_cfg.clks_size; i++)
if (clock_control_on(clk_dev, (clock_control_subsys_t *)
&host_sub_cfg.clks_list[i]) != 0) {
return -EIO;
}
for (i = 0; i < host_sub_cfg.clks_size; i++) {
int ret;
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
&host_sub_cfg.clks_list[i]);
if (ret < 0)
return ret;
}
/* Configure EC legacy configuration IO base address to 0x4E. */
if (!IS_BIT_SET(inst_mswc->MSWCTL1, NPCX_MSWCTL1_VHCFGA)) {

22
drivers/pwm/pwm_npcx.c
View file

@ -161,6 +161,7 @@ static int pwm_npcx_init(const struct device *dev)
struct pwm_reg *const inst = HAL_INSTANCE(dev);
const struct device *const clk_dev =
device_get_binding(NPCX_CLK_CTRL_NAME);
int ret;
/*
* NPCX PWM modulee mixes byte and word registers together. Make sure
@ -169,17 +170,20 @@ static int pwm_npcx_init(const struct device *dev)
*/
NPCX_REG_WORD_ACCESS_CHECK(inst->PRSC, 0xA55A);
/* Turn on device clock first and get source clock freq of it. */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *)&config->clk_cfg) != 0) {
LOG_ERR("Turn on PWM clock fail.");
return -EIO;
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on PWM clock fail %d", ret);
return ret;
}
if (clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg, &data->cycles_per_sec) != 0) {
LOG_ERR("Get PWM clock rate error.");
return -EIO;
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg, &data->cycles_per_sec);
if (ret < 0) {
LOG_ERR("Get PWM clock rate error %d", ret);
return ret;
}
/* Configure PWM device initially */

19
drivers/serial/uart_npcx.c
View file

@ -294,20 +294,25 @@ static int uart_npcx_init(const struct device *dev)
const struct device *const clk_dev =
device_get_binding(NPCX_CLK_CTRL_NAME);
uint32_t uart_rate;
int ret;
/* Turn on device clock first */
if (clock_control_on(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg) != 0) {
return -EIO;
/* Turn on device clock first and get source clock freq. */
ret = clock_control_on(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on UART clock fail %d", ret);
return ret;
}
/*
* If apb2's clock is not 15MHz, we need to find the other optimized
* values of UPSR and UBAUD for baud rate 115200.
*/
if (clock_control_get_rate(clk_dev,
(clock_control_subsys_t *) &config->clk_cfg, &uart_rate) < 0) {
LOG_ERR("UART clock rate get error.");
ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *)
&config->clk_cfg, &uart_rate);
if (ret < 0) {
LOG_ERR("Get UART clock rate error %d", ret);
return ret;
}
__ASSERT(uart_rate == 15000000, "Unsupported apb2 clock for UART!");

2
include/dt-bindings/clock/npcx_clock.h
View file

@ -27,6 +27,6 @@
#define NPCX_PWDWN_CTL6 5
#define NPCX_PWDWN_CTL7 6
#define NPCX_PWDWN_CTL8 7
#define NPCX_PWDWN_CTL_NONE 8
#define NPCX_PWDWN_CTL_COUNT 8
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCX_CLOCK_H_ */