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arm: mps_an521: Add support for the AN521 on MPS2+

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The AN521 is a Soft Macro Model implementation of the SSE-200 subsystem
with SIE-200 and CMSDK components targeting the MPS2+ board. The
SSE-200 subsystem implements two Cortex-M33 cores.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This commit is contained in:
Kumar Gala 2019-05-06 16:56:38 +08:00 • committed by Kumar Gala
commit 502094b096
20 changed files with 1272 additions and 5 deletions
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boards/arm/mps2_an521/CMakeLists.txt Normal file
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#
# Copyright (c) 2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_library()
zephyr_library_sources(pinmux.c)
zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)

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boards/arm/mps2_an521/Kconfig.board Normal file
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#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
config BOARD_MPS2_AN521
bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521)"
depends on SOC_SERIES_MPS2

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boards/arm/mps2_an521/Kconfig.defconfig Normal file
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#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if BOARD_MPS2_AN521
if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE
config BOARD
default "mps2_an521"
endif
if TRUSTED_EXECUTION_NONSECURE
config BOARD
default "mps2_an521_nonsecure"
endif
if GPIO
config GPIO_CMSDK_AHB
def_bool y
config GPIO_CMSDK_AHB_PORT0
def_bool y
config GPIO_CMSDK_AHB_PORT1
def_bool y
config GPIO_CMSDK_AHB_PORT2
def_bool y
config GPIO_CMSDK_AHB_PORT3
def_bool y
endif # GPIO
if PINMUX
config PINMUX_MPS2
def_bool y
endif # PINMUX
if SERIAL
config UART_CMSDK_APB
def_bool y
config UART_INTERRUPT_DRIVEN
def_bool y
endif # SERIAL
if WATCHDOG
config WDOG_CMSDK_APB
def_bool y
endif # WATCHDOG
if COUNTER
if TIMER_TMR_CMSDK_APB
config TIMER_TMR_CMSDK_APB_0
def_bool y
config TIMER_TMR_CMSDK_APB_1
def_bool y
endif # TIMER_TMR_CMSDK_APB
if TIMER_DTMR_CMSDK_APB
config TIMER_DTMR_CMSDK_APB_0
def_bool y
endif # TIMER_DTMR_CMSDK_APB
endif # COUNTER
if I2C
config I2C_SBCON
def_bool y
endif # I2C
endif

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boards/arm/mps2_an521/board.h Normal file
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/*
* Copyright (c) 2018-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
#include <soc.h>
#if defined(CONFIG_GPIO_MMIO32)
/* USERLED0 */
#define LED0_GPIO_PORT FPGAIO_LED0_GPIO_NAME
#define LED0_GPIO_PIN FPGAIO_LED0_USERLED0
/* USERLED1 */
#define LED1_GPIO_PORT FPGAIO_LED0_GPIO_NAME
#define LED1_GPIO_PIN FPGAIO_LED0_USERLED1
/* USERPB0 */
#define SW0_GPIO_NAME FPGAIO_BUTTON_GPIO_NAME
#define SW0_GPIO_PIN FPGAIO_BUTTON_USERPB0
/* USERPB1 */
#define SW1_GPIO_NAME FPGAIO_BUTTON_GPIO_NAME
#define SW1_GPIO_PIN FPGAIO_BUTTON_USERPB1
#endif /* CONFIG_GPIO_MMIO32 */
#endif /* __INC_BOARD_H */

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boards/arm/mps2_an521/doc/index.rst Normal file
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.. _mps2_an521_board:
ARM MPS2+ AN521
###############
Overview
********
The mps2_an521 board configuration is used by Zephyr applications that run
on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
CPU and the following devices:
- Nested Vectored Interrupt Controller (NVIC)
- System Tick System Clock (SYSTICK)
- Cortex-M System Design Kit GPIO
- Cortex-M System Design Kit UART
.. image:: img/mps2_an521.png
:width: 666px
:align: center
:height: 546px
:alt: ARM MPS2+ AN521
More information about the board can be found at the `MPS2 FPGA Website`_.
Hardware
********
ARM MPS2+ AN521 provides the following hardware components:
- ARM Cortex-M33
- Soft Macro Model (SMM) implementation of SSE-200 subsystem
- Memory
- 16MB internal memory SRAM
- 8KB of NVM code
- 224MB code memory
- Debug
- P-JTAG, SWD & 16-bit TRACE
- UART port
- Interface
- AHB GPIO connected to the EXP port
- UART
- SPI
- I2C
- I2S
- Color LCD serial interface
- Ethernet
- VGA
- On-board Peripherals
- Color LCD
- 8 LEDs
- 8 Switches
- External SSRAM1, SSRAM2 & SSRAM3
- SMSC9220
- CS42L52
User push buttons
=================
The mps2_an521 board provides the following user push buttons:
- ON power on
- nSRST: Cortex-M33 system reset and CoreSight debug reset
- USERPB0 and USERPB1: User defined buttons
Supported Features
===================
The mps2_an521 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| TIMER | on-chip | timer |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by the port.
See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware
features.
The default configuration can be found in the defconfig file:
``boards/arm/mps2_an521/mps2_an521_defconfig``.
Interrupt Controller
====================
MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
A Cortex-M33-based board uses vectored exceptions. This means each exception
calls a handler directly from the vector table.
Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed
in the following table:
+------+------------+----------------+--------------------------+
| Exc# | Name | Remarks | Used by Zephyr Kernel |
+======+============+================+==========================+
| 1 | Reset | | system initialization |
+------+------------+----------------+--------------------------+
| 2 | NMI | | system fatal error |
+------+------------+----------------+--------------------------+
| 3 | Hard fault | | system fatal error |
+------+------------+----------------+--------------------------+
| 4 | MemManage | MPU fault | system fatal error |
+------+------------+----------------+--------------------------+
| 5 | Bus | | system fatal error |
+------+------------+----------------+--------------------------+
| 6 | Usage | Undefined | system fatal error |
| | fault | instruction, | |
| | | or switch | |
| | | attempt to ARM | |
| | | mode | |
+------+------------+----------------+--------------------------+
| 7 |SecureFault | Unauthorized | system fatal error |
| | | access to | |
| | | secure region | |
| | | from ns space | |
+------+------------+----------------+--------------------------+
| 8 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 9 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 10 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 11 | SVC | | context switch and |
| | | | software interrupts |
+------+------------+----------------+--------------------------+
| 12 | Debug | | system fatal error |
| | monitor | | |
+------+------------+----------------+--------------------------+
| 13 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 14 | PendSV | | context switch |
+------+------------+----------------+--------------------------+
| 15 | SYSTICK | | system clock |
+------+------------+----------------+--------------------------+
| 16 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 17 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
| 18 | Reserved | | not handled |
+------+------------+----------------+--------------------------+
Pin Mapping
===========
The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16
bits of IO. These controllers are responsible for pin-muxing, input/output,
pull-up, etc.
All GPIO controller pins are exposed via the following sequence of pin numbers:
- Pins 0 - 15 are for GPIO0
- Pins 16 - 31 are for GPIO1
- Pins 32 - 47 are for GPIO2
- Pins 48 - 51 are for GPIO3
Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers:
.. hlist::
:columns: 3
- D0 : EXT_0
- D1 : EXT_4
- D2 : EXT_2
- D3 : EXT_3
- D4 : EXT_1
- D5 : EXT_6
- D6 : EXT_7
- D7 : EXT_8
- D8 : EXT_9
- D9 : EXT_10
- D10 : EXT_12
- D11 : EXT_13
- D12 : EXT_14
- D13 : EXT_11
- D14 : EXT_15
- D15 : EXT_5
- D16 : EXT_16
- D17 : EXT_17
- D18 : EXT_18
- D19 : EXT_19
- D20 : EXT_20
- D21 : EXT_21
- D22 : EXT_22
- D23 : EXT_23
- D24 : EXT_24
- D25 : EXT_25
- D26 : EXT_26
- D27 : EXT_30
- D28 : EXT_28
- D29 : EXT_29
- D30 : EXT_27
- D31 : EXT_32
- D32 : EXT_33
- D33 : EXT_34
- D34 : EXT_35
- D35 : EXT_36
- D36 : EXT_38
- D37 : EXT_39
- D38 : EXT_40
- D39 : EXT_44
- D40 : EXT_41
- D41 : EXT_31
- D42 : EXT_37
- D43 : EXT_42
- D44 : EXT_43
- D45 : EXT_45
- D46 : EXT_46
- D47 : EXT_47
- D48 : EXT_48
- D49 : EXT_49
- D50 : EXT_50
- D51 : EXT_51
Peripheral Mapping:
.. hlist::
:columns: 3
- UART_3_RX : D0
- UART_3_TX : D1
- SPI_3_CS : D10
- SPI_3_MOSI : D11
- SPI_3_MISO : D12
- SPI_3_SCLK : D13
- I2C_3_SDA : D14
- I2C_3_SCL : D15
- UART_4_RX : D26
- UART_4_TX : D30
- SPI_4_CS : D36
- SPI_4_MOSI : D37
- SPI_4_MISO : D38
- SPI_4_SCK : D39
- I2C_4_SDA : D40
- I2C_4_SCL : D41
For mode details please refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_.
LED
============
MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC).
.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON.
System Clock
============
MPS2+ AN521 has several clocks connected:
.. hlist::
:columns: 3
- MAINCLK : 20MHz
- SYSCLK : 20MHz
- S32KCLK : 32kHz
- TRACECLK : 20MHz
- SWCLKTCK : 20MHz
- TRACECLKIN : 20MHz
Serial Port
===========
The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses
UART0, which is J10 on the board.
UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports.
Security components
===================
- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define
secure and non-secure memory maps. By default, all of the memory space is
defined to be secure accessible only
- Secure and Non-secure peripherals via the Peripheral Protection Controller
(PPC). Peripherals can be assigned as secure or non-secure accessible
- Secure boot
- Secure `AMBA®`_ interconnect
Serial Configuration Controller (SCC)
=====================================
The MPS2+ AN521 implements a Serial Configuration Control (SCC) register.
The purpose of this register is to allow individual control of clocks,
reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and
switches.
Programming and Debugging
*************************
MPS2+ AN521 supports the v8m security extension, and by default boots to the
secure state.
When building a secure/non-secure application, the secure application will
have to set the idau/sau and mpc configuration to permit access from the
non-secure application before jumping.
The following system components are required to be properly configured during the
secure firmware:
- AHB5 TrustZone Memory Protection Controller (MPC)
- AHB5 TrustZone Peripheral Protection Controller (PPC)
- Implementation-Defined Attribution Unit (IDAU)
For more details please refer to `Corelink SSE-200 Subsystem`_.
Flashing
========
MPS2+ AN521 provides:
- A USB connection to the host computer, which exposes a Mass Storage
- A Serial Port which is J10 on MPS2+ board
Building a secure only application
----------------------------------
You can build applications in the usual way. Here is an example for
the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mps2_an521
:goals: build
Open a serial terminal (minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Reset the board, and you should see the following message on the corresponding
serial port:
.. code-block:: console
Hello World! mps2_an521
Building a secure/non-secure with Trusted Firmware
--------------------------------------------------
The process requires five steps:
1. Build Trusted Firmware (tfm).
2. Import it as a library to the Zephyr source folder.
3. Build Zephyr with a non-secure configuration.
4. Merge the two binaries together and sign them.
5. Concatenate the bootloader with the signed image blob.
In order to build tfm please refer to `Trusted Firmware M Guide`_.
Follow the build steps for AN521 target while replacing the platform with
``-DTARGET_PLATFORM=AN521`` and compiler (if required) with ``-DCOMPILER=GNUARM``
Copy over tfm as a library to the Zephyr project source and create a shortcut
for the secure veneers.
.. code-block:: bash
cp -r install/ $ZEPHYR_PROJECT/src/ext
cp $ZEPHYR_PROJECT/src/ext/install/export/tfm/veneers/s_veneers.o $ZEPHYR_PROJECT/src/ext
Build the Zephyr app in the usual way.
Uploading an application to MPS2+ AN521
---------------------------------------
Applications can be elf, hex or bin format. The binaries were flashed while
the board boot up, all files were stored in the on-board Micro SD card in
advance. The Motherboard Configuration Controller (MCC) will responsible for
loading the FPGA image and binaries.
Connect the MPS2+ to your host computer using the USB port. You should see a
USB connection exposing a Mass Storage (``V2M_MPS2`` by default).
The update needs 3 steps:
1. Copy application files to ``<MPS2 device name>/SOFTWARE/``.
2. Open ``<MPS2 device name>/MB/HBI0263C/AN521/images.txt``.
3. Update the ``AN521/images.txt`` file as follows:
.. code-block:: bash
TITLE: Versatile Express Images Configuration File
[IMAGES]
TOTALIMAGES: 1 ;Number of Images (Max: 32)
IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program
IMAGE0FILE: \SOFTWARE\zephyr.bin
Reset the board, and you should see the following message on the corresponding
serial port:
.. code-block:: console
Hello World! mps2_an521
.. _MPS2 FPGA Website:
https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2
.. _MPS2+ AN521 Technical Reference Manual (TRM):
http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/DAI0521C_Example_SSE200_Subsystem_for_MPS2plus.pdf
.. _Cortex M33 Generic User Guide:
http://infocenter.arm.com/help/topic/com.arm.doc.100235_0004_00_en/arm_cortex_m33_dgug_100235_0004_00_en.pdf
.. _Trusted Firmware M Guide:
https://git.trustedfirmware.org/trusted-firmware-m.git/tree/docs/user_guides/tfm_build_instruction.rst
.. _Corelink SSE-200 Subsystem:
https://developer.arm.com/products/system-design/subsystems/corelink-sse-200-subsystem
.. _IDAU:
https://developer.arm.com/products/architecture/cpu-architecture/m-profile/docs/100690/latest/attribution-units-sau-and-idau
.. _AMBA®:
https://developer.arm.com/products/architecture/system-architectures/amba

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boards/arm/mps2_an521/mps2_an521-common.dtsi Normal file
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/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
timer0: timer@0 {
compatible = "arm,cmsdk-timer";
reg = <0x0 0x1000>;
interrupts = <3 3>;
};
timer1: timer@1000 {
compatible = "arm,cmsdk-timer";
reg = <0x1000 0x1000>;
interrupts = <4 3>;
};
dtimer0: dtimer@2000 {
compatible = "arm,cmsdk-dtimer";
reg = <0x2000 0x1000>;
interrupts = <5 3>;
};
mhu0: mhu@3000 {
compatible = "arm,mhu";
reg = <0x3000 0x1000>;
interrupts = <6 3>;
label = "MHU_0";
};
mhu1: mhu@4000 {
compatible = "arm,mhu";
reg = <0x4000 0x1000>;
interrupts = <7 3>;
label = "MHU_1";
};
gpio0: gpio@100000 {
compatible = "arm,cmsdk-gpio";
reg = <0x100000 0x1000>;
interrupts = <68 3>;
};
gpio1: gpio@101000 {
compatible = "arm,cmsdk-gpio";
reg = <0x101000 0x1000>;
interrupts = <69 3>;
};
gpio2: gpio@102000 {
compatible = "arm,cmsdk-gpio";
reg = <0x102000 0x1000>;
interrupts = <70 3>;
};
gpio3: gpio@103000 {
compatible = "arm,cmsdk-gpio";
reg = <0x103000 0x1000>;
interrupts = <71 3>;
};
wdog0: wdog@81000 {
compatible = "arm,cmsdk-watchdog";
reg = <0x81000 0x1000>;
};
uart0: uart@200000 {
compatible = "arm,cmsdk-uart";
reg = <0x200000 0x1000>;
interrupts = <33 3 32 3>;
interrupt-names = "tx", "rx";
current-speed = <115200>;
label = "UART_0";
};
uart1: uart@201000 {
compatible = "arm,cmsdk-uart";
reg = <0x201000 0x1000>;
interrupts = <35 3 34 3>;
interrupt-names = "tx", "rx";
current-speed = <115200>;
label = "UART_1";
};
uart2: uart@202000 {
compatible = "arm,cmsdk-uart";
reg = <0x202000 0x1000>;
interrupts = <37 3 36 3>;
interrupt-names = "tx", "rx";
current-speed = <115200>;
label = "UART_2";
};
uart3: uart@203000 {
compatible = "arm,cmsdk-uart";
reg = <0x203000 0x1000>;
interrupts = <39 3 38 3>;
interrupt-names = "tx", "rx";
current-speed = <115200>;
label = "UART_3";
};
uart4: uart@204000 {
compatible = "arm,cmsdk-uart";
reg = <0x204000 0x1000>;
interrupts = <41 3 40 3>;
interrupt-names = "tx", "rx";
current-speed = <115200>;
label = "UART_4";
};
i2c_touch: i2c@207000 {
compatible = "arm,versatile-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x207000 0x1000>;
label = "I2C_TOUCH";
};
i2c_audio_conf: i2c@208000 {
compatible = "arm,versatile-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x208000 0x1000>;
label = "I2C_AUDIO_CONF";
};
i2c_shield0: i2c@20c000 {
compatible = "arm,versatile-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20c000 0x1000>;
label = "I2C_SHIELD0";
};
i2c_shield1: i2c@20d000 {
compatible = "arm,versatile-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20d000 0x1000>;
label = "I2C_SHIELD1";
};

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/*
* Copyright (c) 2018-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
/ {
compatible = "arm,mps2";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
sram0: memory@30000000 {
compatible = "mmio-sram";
reg = <0x30000000 0x1000000>;
};
flash0: flash@10000000 {
reg = <0x10000000 0xE000000>;
};
soc {
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
#include "mps2_an521-common.dtsi"
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

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boards/arm/mps2_an521/mps2_an521.yaml Normal file
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identifier: mps2_an521
name: ARM V2M MPS2-AN521
type: mcu
arch: arm
toolchain:
- gnuarmemb
- zephyr
- xtools

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#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_ARM=y
CONFIG_SOC_FAMILY_ARM=y
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN521=y
CONFIG_BOARD_MPS2_AN521=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# PinMuxing
CONFIG_PINMUX=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CMSDK_APB=y
# Watchdog
CONFIG_WATCHDOG=y
CONFIG_I2C=y

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/*
* Copyright (c) 2018-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
/ {
compatible = "arm,mps2";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
sram0: memory@28100000 {
compatible = "mmio-sram";
reg = <0x28100000 0x100000>;
};
flash0: flash@100000 {
reg = <0x100000 0xDF00000>;
};
soc {
peripheral@40000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#include "mps2_an521-common.dtsi"
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

8
boards/arm/mps2_an521/mps2_an521_nonsecure.yaml Normal file
View file

@ -0,0 +1,8 @@
identifier: mps2_an521_nonsecure
name: ARM V2M MPS2-AN521_nonsecure
type: mcu
arch: arm
toolchain:
- gnuarmemb
- zephyr
- xtools

33
boards/arm/mps2_an521/mps2_an521_nonsecure_defconfig Normal file
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@ -0,0 +1,33 @@
#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_ARM=y
CONFIG_SOC_FAMILY_ARM=y
CONFIG_SOC_SERIES_MPS2=y
CONFIG_SOC_MPS2_AN521=y
CONFIG_BOARD_MPS2_AN521=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_RUNTIME_NMI=y
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# PinMuxing
CONFIG_PINMUX=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CMSDK_APB=y
# Watchdog
CONFIG_WATCHDOG=y
CONFIG_I2C=y

168
boards/arm/mps2_an521/pinmux.c Normal file
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@ -0,0 +1,168 @@
/*
* Copyright (c) 2018-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <device.h>
#include <init.h>
#include <kernel.h>
#include <pinmux.h>
#include <soc.h>
#include <sys_io.h>
#include <gpio/gpio_cmsdk_ahb.h>
#include "pinmux/pinmux.h"
/**
* @brief Pinmux driver for ARM MPS2 AN521 Board
*
* The ARM MPS2 AN521 Board has 4 GPIO controllers. These controllers
* are responsible for pin muxing, input/output, pull-up, etc.
*
* All GPIO controller pins are exposed via the following sequence of pin
* numbers:
* Pins 0 - 15 are for GPIO0
* Pins 16 - 31 are for GPIO1
* Pins 32 - 47 are for GPIO2
* Pins 48 - 51 are for GPIO3
*
* For the GPIO controllers configuration ARM MPS2 AN521 Board follows the
* Arduino compliant pin out.
*/
#define CMSDK_AHB_GPIO0_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0)
#define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1)
#define CMSDK_AHB_GPIO2_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2)
#define CMSDK_AHB_GPIO3_DEV \
((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3)
/*
* This is the mapping from the ARM MPS2 AN521 Board pins to GPIO
* controllers.
*
* D0 : EXT_0
* D1 : EXT_4
* D2 : EXT_2
* D3 : EXT_3
* D4 : EXT_1
* D5 : EXT_6
* D6 : EXT_7
* D7 : EXT_8
* D8 : EXT_9
* D9 : EXT_10
* D10 : EXT_12
* D11 : EXT_13
* D12 : EXT_14
* D13 : EXT_11
* D14 : EXT_15
* D15 : EXT_5
* D16 : EXT_16
* D17 : EXT_17
* D18 : EXT_18
* D19 : EXT_19
* D20 : EXT_20
* D21 : EXT_21
* D22 : EXT_22
* D23 : EXT_23
* D24 : EXT_24
* D25 : EXT_25
* D26 : EXT_26
* D27 : EXT_30
* D28 : EXT_28
* D29 : EXT_29
* D30 : EXT_27
* D31 : EXT_32
* D32 : EXT_33
* D33 : EXT_34
* D34 : EXT_35
* D35 : EXT_36
* D36 : EXT_38
* D37 : EXT_39
* D38 : EXT_40
* D39 : EXT_44
* D40 : EXT_41
* D41 : EXT_31
* D42 : EXT_37
* D43 : EXT_42
* D44 : EXT_43
* D45 : EXT_45
* D46 : EXT_46
* D47 : EXT_47
* D48 : EXT_48
* D49 : EXT_49
* D50 : EXT_50
* D51 : EXT_51
*
* UART_3_RX : D0
* UART_3_TX : D1
* SPI_3_CS : D10
* SPI_3_MOSI : D11
* SPI_3_MISO : D12
* SPI_3_SCLK : D13
* I2C_3_SDA : D14
* I2C_3_SCL : D15
* UART_4_RX : D26
* UART_4_TX : D30
* SPI_4_CS : D36
* SPI_4_MOSI : D37
* SPI_4_MISO : D38
* SPI_4_SCK : D39
* I2C_4_SDA : D40
* I2C_4_SCL : D41
*
*/
static void arm_mps2_pinmux_defaults(void)
{
u32_t gpio_0 = 0;
u32_t gpio_1 = 0;
u32_t gpio_2 = 0;
/* Set GPIO Alternate Functions */
gpio_0 = (1<<0) /* Shield 0 UART 3 RXD */
| (1<<4) /* Shield 0 UART 3 TXD */
| (1<<5) /* Shield 0 I2C SCL SBCON2 */
| (1<<15) /* Shield 0 I2C SDA SBCON2 */
| (1<<11) /* Shield 0 SPI 3 SCK */
| (1<<12) /* Shield 0 SPI 3 SS */
| (1<<13) /* Shield 0 SPI 3 MOSI */
| (1<<14); /* Shield 0 SPI 3 MISO */
CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0;
gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */
| (1<<14) /* Shield 1 UART 4 TXD */
| (1<<15) /* Shield 1 I2C SCL SBCON3 */
| (1<<0) /* ADC SPI 2 SS */
| (1<<1) /* ADC SPI 2 MISO */
| (1<<2) /* ADC SPI 2 MOSI */
| (1<<3) /* ADC SPI 2 SCK */
| (1<<5) /* USER BUTTON 0 */
| (1<<6); /* USER BUTTON 1 */
CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1;
gpio_2 = (1<<9) /* Shield 1 I2C SDA SBCON3 */
| (1<<6) /* Shield 1 SPI 4 SS */
| (1<<7) /* Shield 1 SPI 4 MOSI */
| (1<<8) /* Shield 1 SPI 4 MISO */
| (1<<12); /* Shield 1 SPI 4 SCK */
CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2;
}
static int arm_mps2_pinmux_init(struct device *port)
{
ARG_UNUSED(port);
arm_mps2_pinmux_defaults();
return 0;
}
SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

16
soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 Normal file
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@ -0,0 +1,16 @@
#
# Copyright (c) 2018-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_MPS2_AN521
config SOC
default "mps2_an521"
config NUM_IRQS
int
default 96
endif

8
soc/arm/arm/mps2/Kconfig.soc
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2017 Linaro Limited
# Copyright (c) 2017-2019 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
@ -13,4 +13,10 @@ config SOC_MPS2_AN385
select CPU_CORTEX_M3
select CPU_HAS_ARM_MPU
config SOC_MPS2_AN521
bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521)"
select CPU_CORTEX_M33
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
endchoice

15
soc/arm/arm/mps2/arm_mpu_regions.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2017-2019 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,15 +9,24 @@
#include <soc.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
#if defined(CONFIG_ARMV8_M_BASELINE) || \
defined(CONFIG_ARMV8_M_MAINLINE)
#define MPS2_FLASH_ATTR REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE*1024)
#define MPS2_RAM_ATTR REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE*1024)
#else
#define MPS2_FLASH_ATTR REGION_FLASH_ATTR(REGION_4M)
#define MPS2_RAM_ATTR REGION_RAM_ATTR(REGION_2M)
#endif
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_4M)),
MPS2_FLASH_ATTR),
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_2M))
MPS2_RAM_ATTR)
};
const struct arm_mpu_config mpu_config = {

69
soc/arm/arm/mps2/dts_fixup.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (c) 2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#if defined(CONFIG_SOC_MPS2_AN521)
/* SoC level DTS fixup file */
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_NUM_MPU_REGIONS DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
#if defined (CONFIG_ARM_NONSECURE_FIRMWARE)
/* CMSDK APB Timers */
#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS
#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0
#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS
#define DT_CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0
/* CMSDK APB Dual Timer */
#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS
#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40100000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40100000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40101000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40101000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40102000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40102000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40103000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40103000_IRQ_0
#else
/* CMSDK APB Timers */
#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_50000000_BASE_ADDRESS
#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_50000000_IRQ_0
#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_50001000_BASE_ADDRESS
#define DT_CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_50001000_IRQ_0
/* CMSDK APB Dual Timer */
#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_50002000_BASE_ADDRESS
#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_50002000_IRQ_0
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_50100000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_50100000_IRQ_0
#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_50101000_BASE_ADDRESS
#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_50101000_IRQ_0
#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_50102000_BASE_ADDRESS
#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_50102000_IRQ_0
#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_50103000_BASE_ADDRESS
#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_50103000_IRQ_0
#endif
#endif /* CONFIG_SOC_MPS2_AN521 */
/* End of SoC Level DTS fixup file */

37
soc/arm/arm/mps2/soc.c
View file

@ -20,6 +20,43 @@ GPIO_MMIO32_INIT(fpgaio_button, FPGAIO_BUTTON_GPIO_NAME,
GPIO_MMIO32_INIT(fpgaio_misc, FPGAIO_MISC_GPIO_NAME,
&__MPS2_FPGAIO->misc, FPGAIO_MISC_MASK);
/* (Secure System Control) Base Address */
#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL)
#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL)
#define NON_SECURE_FLASH_ADDRESS (0x100000)
#define NON_SECURE_FLASH_OFFSET (0x10000000)
/**
* @brief Wake up CPU 1 from another CPU, this is plaform specific.
*
*/
void wakeup_cpu1(void)
{
/* Set the Initial Secure Reset Vector Register for CPU 1 */
*(u32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) =
CONFIG_FLASH_BASE_ADDRESS +
NON_SECURE_FLASH_ADDRESS -
NON_SECURE_FLASH_OFFSET;
/* Set the CPU Boot wait control after reset */
*(u32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0;
}
/**
* @brief Get the current CPU ID, this is plaform specific.
*
* @return Current CPU ID
*/
u32_t sse_200_platform_get_cpu_id(void)
{
volatile u32_t *p_cpu_id = (volatile u32_t *)SSE_200_CPU_ID_UNIT_BASE;
return (u32_t)*p_cpu_id;
}
/**
* @brief Perform basic hardware initialization at boot.
*

13
soc/arm/arm/mps2/soc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2017-2019 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,6 +8,17 @@
#define _SOC_H_
#define __MPU_PRESENT 1
#if defined(CONFIG_SOC_MPS2_AN521)
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
#define __DSP_PRESENT 1U /* DSP extension present */
#endif
#include <soc_devices.h>
extern void wakeup_cpu1(void);
extern u32_t sse_200_platform_get_cpu_id(void);
#endif /* _SOC_H_ */