diff --git a/drivers/nble/gap.c b/drivers/nble/gap.c
index d219af52174..61d2687be8d 100644
--- a/drivers/nble/gap.c
+++ b/drivers/nble/gap.c
@@ -29,6 +29,7 @@
 
 #define NBLE_SWDIO_PIN	6
 #define NBLE_RESET_PIN	NBLE_SWDIO_PIN
+#define NBLE_BTWAKE_PIN 5
 
 #define NBLE_CHANNEL	0
 
@@ -89,6 +90,18 @@ int bt_enable(bt_ready_cb_t cb)
 		return -EINVAL;
 	}
 
+	ret = gpio_pin_configure(gpio, NBLE_BTWAKE_PIN, GPIO_DIR_OUT);
+	if (ret) {
+		BT_ERR("Error configuring pin %d", NBLE_BTWAKE_PIN);
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_write(gpio, NBLE_BTWAKE_PIN, 1);
+	if (ret) {
+		BT_ERR("Error pin write %d", NBLE_BTWAKE_PIN);
+		return -EINVAL;
+	}
+
 	/**
 	 * NBLE reset is achieved by asserting low the SWDIO pin.
 	 * However, the BLE Core chip can be in SWD debug mode,