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drivers: pwm: nrf_sw: drop broken runtime timer clock scaling

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There is some kind of runtime clock scaling implemented when period
cycles exceed 16-bit value. This is broken, because configured PWM has
far higher frequency in that case. Replace that mechanism with simply
veryfying if requested PWM period does not exceed 16-bit value.

Suggested-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This commit is contained in:
Marcin Niestroj 2020-10-26 22:28:10 +01:00 • committed by Carles Cufí
commit 4f868cd9fa
1 changed files with 12 additions and 10 deletions
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22
drivers/pwm/pwm_nrf5_sw.c
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@ -98,7 +98,6 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
struct pwm_data *data;
uint8_t ppi_index;
uint8_t channel;
uint16_t div;
uint32_t ret;
config = (const struct pwm_config *)dev->config;
@ -120,6 +119,15 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
return ret;
}
/* TODO: if the assigned NRF_TIMER supports higher bit resolution,
* use that info in config struct.
*/
if (period_cycles > BIT_MASK(16)) {
LOG_ERR("Too long period (%u), adjust pwm prescaler!",
period_cycles);
return -EINVAL;
}
/* map pwm pin to GPIOTE config/channel */
channel = pwm_channel_map(data, config->map_size, pwm);
if (channel >= config->map_size) {
@ -154,18 +162,12 @@ static int pwm_nrf5_sw_pin_set(const struct device *dev, uint32_t pwm,
nrf_gpio_pin_clear(pwm);
}
/* TODO: if the assigned NRF_TIMER supports higher bit resolution,
* use that info in config struct and setup accordingly.
*/
/* calc div, to scale down to fit in 16 bits */
div = period_cycles >> 16;
/* configure TIMER */
timer->EVENTS_COMPARE[channel] = 0;
timer->EVENTS_COMPARE[config->map_size] = 0;
timer->CC[channel] = pulse_cycles >> div;
timer->CC[config->map_size] = period_cycles >> div;
timer->CC[channel] = pulse_cycles;
timer->CC[config->map_size] = period_cycles;
timer->TASKS_CLEAR = 1;
/* configure GPIOTE, toggle with initialise output high */