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kernel: rename z_arch_ to arch_

Browse source 
Promote the private z_arch_* namespace, which specifies
the interface between the core kernel and the
architecture code, to a new top-level namespace named
arch_*.

This allows our documentation generation to create
online documentation for this set of interfaces,
and this set of interfaces is worth treating in a
more formal way anyway.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-11-07 12:43:29 -08:00 • committed by Andrew Boie
commit 4f77c2ad53
178 changed files with 912 additions and 910 deletions
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34
include/arch/arc/arch.h
View file

@ -89,10 +89,10 @@ extern "C" {
#if defined(CONFIG_USERSPACE)
#define Z_ARCH_THREAD_STACK_RESERVED \
#define ARCH_THREAD_STACK_RESERVED \
(STACK_GUARD_SIZE + CONFIG_PRIVILEGED_STACK_SIZE)
#else
#define Z_ARCH_THREAD_STACK_RESERVED (STACK_GUARD_SIZE)
#define ARCH_THREAD_STACK_RESERVED (STACK_GUARD_SIZE)
#endif
@ -107,8 +107,8 @@ extern "C" {
* MPU start, size alignment
*/
#define Z_ARC_THREAD_STACK_ALIGN(size) Z_ARC_MPUV2_SIZE_ALIGN(size)
#define Z_ARCH_THREAD_STACK_LEN(size) \
(Z_ARC_MPUV2_SIZE_ALIGN(size) + Z_ARCH_THREAD_STACK_RESERVED)
#define ARCH_THREAD_STACK_LEN(size) \
(Z_ARC_MPUV2_SIZE_ALIGN(size) + ARCH_THREAD_STACK_RESERVED)
/*
* for stack array, each array member should be aligned both in size
* and start
@ -116,7 +116,7 @@ extern "C" {
#define Z_ARC_THREAD_STACK_ARRAY_LEN(size) \
(Z_ARC_MPUV2_SIZE_ALIGN(size) + \
MAX(Z_ARC_MPUV2_SIZE_ALIGN(size), \
POW2_CEIL(Z_ARCH_THREAD_STACK_RESERVED)))
POW2_CEIL(ARCH_THREAD_STACK_RESERVED)))
#else
/*
* MPUv3, no-mpu and no USERSPACE share the same macro definitions.
@ -130,33 +130,33 @@ extern "C" {
* aligned
*/
#define Z_ARC_THREAD_STACK_ALIGN(size) (STACK_ALIGN)
#define Z_ARCH_THREAD_STACK_LEN(size) \
(STACK_SIZE_ALIGN(size) + Z_ARCH_THREAD_STACK_RESERVED)
#define ARCH_THREAD_STACK_LEN(size) \
(STACK_SIZE_ALIGN(size) + ARCH_THREAD_STACK_RESERVED)
#define Z_ARC_THREAD_STACK_ARRAY_LEN(size) \
Z_ARCH_THREAD_STACK_LEN(size)
ARCH_THREAD_STACK_LEN(size)
#endif /* CONFIG_USERSPACE && CONFIG_ARC_MPU_VER == 2 */
#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
#define ARCH_THREAD_STACK_DEFINE(sym, size) \
struct _k_thread_stack_element __noinit \
__aligned(Z_ARC_THREAD_STACK_ALIGN(size)) \
sym[Z_ARCH_THREAD_STACK_LEN(size)]
sym[ARCH_THREAD_STACK_LEN(size)]
#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
#define ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
struct _k_thread_stack_element __noinit \
__aligned(Z_ARC_THREAD_STACK_ALIGN(size)) \
sym[nmemb][Z_ARC_THREAD_STACK_ARRAY_LEN(size)]
#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
#define ARCH_THREAD_STACK_MEMBER(sym, size) \
struct _k_thread_stack_element \
__aligned(Z_ARC_THREAD_STACK_ALIGN(size)) \
sym[Z_ARCH_THREAD_STACK_LEN(size)]
sym[ARCH_THREAD_STACK_LEN(size)]
#define Z_ARCH_THREAD_STACK_SIZEOF(sym) \
(sizeof(sym) - Z_ARCH_THREAD_STACK_RESERVED)
#define ARCH_THREAD_STACK_SIZEOF(sym) \
(sizeof(sym) - ARCH_THREAD_STACK_RESERVED)
#define Z_ARCH_THREAD_STACK_BUFFER(sym) \
#define ARCH_THREAD_STACK_BUFFER(sym) \
((char *)(sym))
#ifdef CONFIG_ARC_MPU
@ -227,7 +227,7 @@ extern "C" {
/* Typedef for the k_mem_partition attribute*/
typedef u32_t k_mem_partition_attr_t;
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}

2
include/arch/arc/arch_inlines.h
View file

@ -16,7 +16,7 @@
#include <arch/arc/v2/aux_regs.h>
#endif
static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void)
static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
{
#ifdef CONFIG_SMP
u32_t core;

38
include/arch/arc/syscall.h
View file

@ -38,10 +38,10 @@ extern "C" {
* just for enabling CONFIG_USERSPACE on arc w/o errors.
*/
static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -63,10 +63,10 @@ static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -87,9 +87,9 @@ static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -109,9 +109,9 @@ static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -129,8 +129,8 @@ static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -147,7 +147,7 @@ static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r6 __asm__("r6") = call_id;
@ -163,7 +163,7 @@ static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id
return ret;
}
static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
{
register u32_t ret __asm__("r0");
register u32_t r6 __asm__("r6") = call_id;
@ -179,7 +179,7 @@ static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
return ret;
}
static inline bool z_arch_is_user_context(void)
static inline bool arch_is_user_context(void)
{
u32_t status;

2
include/arch/arc/v2/error.h
View file

@ -25,7 +25,7 @@ extern "C" {
/*
* use trap_s to raise a SW exception
*/
#define Z_ARCH_EXCEPT(reason_p) do { \
#define ARCH_EXCEPT(reason_p) do { \
__asm__ volatile ( \
"mov r0, %[reason]\n\t" \
"trap_s %[id]\n\t" \

32
include/arch/arc/v2/irq.h
View file

@ -26,15 +26,15 @@ extern "C" {
#ifdef _ASMLANGUAGE
GTEXT(_irq_exit);
GTEXT(z_arch_irq_enable)
GTEXT(z_arch_irq_disable)
GTEXT(arch_irq_enable)
GTEXT(arch_irq_disable)
GTEXT(z_arc_firq_stack_set)
#else
extern void z_arc_firq_stack_set(void);
extern void z_arch_irq_enable(unsigned int irq);
extern void z_arch_irq_disable(unsigned int irq);
extern int z_arch_irq_is_enabled(unsigned int irq);
extern void arch_irq_enable(unsigned int irq);
extern void arch_irq_disable(unsigned int irq);
extern int arch_irq_is_enabled(unsigned int irq);
extern void _irq_exit(void);
extern void z_irq_priority_set(unsigned int irq, unsigned int prio,
@ -50,7 +50,7 @@ extern void z_irq_spurious(void *unused);
* We additionally set the priority in the interrupt controller at
* runtime.
*/
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
z_irq_priority_set(irq_p, priority_p, flags_p); \
@ -78,7 +78,7 @@ extern void z_irq_spurious(void *unused);
* See include/irq.h for details.
* All arguments must be computable at build time.
*/
#define Z_ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \
BUILD_ASSERT_MSG(priority_p || !IS_ENABLED(CONFIG_ARC_FIRQ) || \
@ -92,14 +92,14 @@ extern void z_irq_spurious(void *unused);
})
static inline void z_arch_isr_direct_header(void)
static inline void arch_isr_direct_header(void)
{
#ifdef CONFIG_TRACING
z_sys_trace_isr_enter();
#endif
}
static inline void z_arch_isr_direct_footer(int maybe_swap)
static inline void arch_isr_direct_footer(int maybe_swap)
{
/* clear SW generated interrupt */
if (z_arc_v2_aux_reg_read(_ARC_V2_ICAUSE) ==
@ -111,16 +111,16 @@ static inline void z_arch_isr_direct_footer(int maybe_swap)
#endif
}
#define Z_ARCH_ISR_DIRECT_HEADER() z_arch_isr_direct_header()
extern void z_arch_isr_direct_header(void);
#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
extern void arch_isr_direct_header(void);
#define Z_ARCH_ISR_DIRECT_FOOTER(swap) z_arch_isr_direct_footer(swap)
#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
/*
* Scheduling can not be done in direct isr. If required, please use kernel
* aware interrupt handling
*/
#define Z_ARCH_ISR_DIRECT_DECLARE(name) \
#define ARCH_ISR_DIRECT_DECLARE(name) \
static inline int name##_body(void); \
__attribute__ ((interrupt("ilink")))void name(void) \
{ \
@ -163,7 +163,7 @@ extern void z_arch_isr_direct_header(void);
* "interrupt disable state" prior to the call.
*/
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key;
@ -171,12 +171,12 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
return key;
}
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
__asm__ volatile("seti %0" : : "ir"(key) : "memory");
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
/* ARC irq lock uses instruction "clri r0",
* r0 == {26’d0, 1’b1, STATUS32.IE, STATUS32.E[3:0] }

2
include/arch/arc/v2/misc.h
View file

@ -23,7 +23,7 @@ extern unsigned int z_arc_cpu_sleep_mode;
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}

28
include/arch/arm/arch.h
View file

@ -189,56 +189,56 @@ extern "C" {
/* Guard is 'carved-out' of the thread stack region, and the supervisor
* mode stack is allocated elsewhere by gen_priv_stack.py
*/
#define Z_ARCH_THREAD_STACK_RESERVED 0
#define ARCH_THREAD_STACK_RESERVED 0
#else
#define Z_ARCH_THREAD_STACK_RESERVED MPU_GUARD_ALIGN_AND_SIZE
#define ARCH_THREAD_STACK_RESERVED MPU_GUARD_ALIGN_AND_SIZE
#endif
#if defined(CONFIG_USERSPACE) && \
defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
#define ARCH_THREAD_STACK_DEFINE(sym, size) \
struct _k_thread_stack_element __noinit \
__aligned(POW2_CEIL(size)) sym[POW2_CEIL(size)]
#else
#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
#define ARCH_THREAD_STACK_DEFINE(sym, size) \
struct _k_thread_stack_element __noinit __aligned(STACK_ALIGN) \
sym[size+MPU_GUARD_ALIGN_AND_SIZE]
#endif
#if defined(CONFIG_USERSPACE) && \
defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define Z_ARCH_THREAD_STACK_LEN(size) (POW2_CEIL(size))
#define ARCH_THREAD_STACK_LEN(size) (POW2_CEIL(size))
#else
#define Z_ARCH_THREAD_STACK_LEN(size) ((size)+MPU_GUARD_ALIGN_AND_SIZE)
#define ARCH_THREAD_STACK_LEN(size) ((size)+MPU_GUARD_ALIGN_AND_SIZE)
#endif
#if defined(CONFIG_USERSPACE) && \
defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
#define ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
struct _k_thread_stack_element __noinit \
__aligned(POW2_CEIL(size)) \
sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
sym[nmemb][ARCH_THREAD_STACK_LEN(size)]
#else
#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
#define ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
struct _k_thread_stack_element __noinit \
__aligned(STACK_ALIGN) \
sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
sym[nmemb][ARCH_THREAD_STACK_LEN(size)]
#endif
#if defined(CONFIG_USERSPACE) && \
defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
#define ARCH_THREAD_STACK_MEMBER(sym, size) \
struct _k_thread_stack_element __aligned(POW2_CEIL(size)) \
sym[POW2_CEIL(size)]
#else
#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
#define ARCH_THREAD_STACK_MEMBER(sym, size) \
struct _k_thread_stack_element __aligned(STACK_ALIGN) \
sym[size+MPU_GUARD_ALIGN_AND_SIZE]
#endif
#define Z_ARCH_THREAD_STACK_SIZEOF(sym) (sizeof(sym) - MPU_GUARD_ALIGN_AND_SIZE)
#define ARCH_THREAD_STACK_SIZEOF(sym) (sizeof(sym) - MPU_GUARD_ALIGN_AND_SIZE)
#define Z_ARCH_THREAD_STACK_BUFFER(sym) \
#define ARCH_THREAD_STACK_BUFFER(sym) \
((char *)(sym) + MPU_GUARD_ALIGN_AND_SIZE)
/* Legacy case: retain containing extern "C" with C++ */

6
include/arch/arm/asm_inline_gcc.h
View file

@ -36,7 +36,7 @@ extern "C" {
* except NMI.
*/
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key;
@ -75,7 +75,7 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
* previously disabled.
*/
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
if (key) {
@ -100,7 +100,7 @@ static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
/* This convention works for both PRIMASK and BASEPRI */
return key == 0;

4
include/arch/arm/error.h
View file

@ -31,7 +31,7 @@ extern "C" {
* schedule a new thread until they are unlocked which is not what we want.
* Force them unlocked as well.
*/
#define Z_ARCH_EXCEPT(reason_p) \
#define ARCH_EXCEPT(reason_p) \
register u32_t r0 __asm__("r0") = reason_p; \
do { \
__asm__ volatile ( \
@ -42,7 +42,7 @@ do { \
: "memory"); \
} while (false)
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
#define Z_ARCH_EXCEPT(reason_p) do { \
#define ARCH_EXCEPT(reason_p) do { \
__asm__ volatile ( \
"eors.n r0, r0\n\t" \
"msr BASEPRI, r0\n\t" \

30
include/arch/arm/irq.h
View file

@ -24,13 +24,13 @@ extern "C" {
#ifdef _ASMLANGUAGE
GTEXT(z_arm_int_exit);
GTEXT(z_arch_irq_enable)
GTEXT(z_arch_irq_disable)
GTEXT(z_arch_irq_is_enabled)
GTEXT(arch_irq_enable)
GTEXT(arch_irq_disable)
GTEXT(arch_irq_is_enabled)
#else
extern void z_arch_irq_enable(unsigned int irq);
extern void z_arch_irq_disable(unsigned int irq);
extern int z_arch_irq_is_enabled(unsigned int irq);
extern void arch_irq_enable(unsigned int irq);
extern void arch_irq_disable(unsigned int irq);
extern int arch_irq_is_enabled(unsigned int irq);
extern void z_arm_int_exit(void);
@ -76,14 +76,14 @@ extern void z_arm_irq_priority_set(unsigned int irq, unsigned int prio,
* We additionally set the priority in the interrupt controller at
* runtime.
*/
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
irq_p; \
})
#define Z_ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \
z_arm_irq_priority_set(irq_p, priority_p, flags_p); \
@ -93,15 +93,15 @@ extern void z_arm_irq_priority_set(unsigned int irq, unsigned int prio,
/* FIXME prefer these inline, but see GH-3056 */
#ifdef CONFIG_SYS_POWER_MANAGEMENT
extern void _arch_isr_direct_pm(void);
#define Z_ARCH_ISR_DIRECT_PM() _arch_isr_direct_pm()
#define ARCH_ISR_DIRECT_PM() _arch_isr_direct_pm()
#else
#define Z_ARCH_ISR_DIRECT_PM() do { } while (false)
#define ARCH_ISR_DIRECT_PM() do { } while (false)
#endif
#define Z_ARCH_ISR_DIRECT_HEADER() z_arch_isr_direct_header()
extern void z_arch_isr_direct_header(void);
#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
extern void arch_isr_direct_header(void);
#define Z_ARCH_ISR_DIRECT_FOOTER(swap) z_arch_isr_direct_footer(swap)
#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
/* arch/arm/core/exc_exit.S */
extern void z_arm_int_exit(void);
@ -110,7 +110,7 @@ extern void z_arm_int_exit(void);
extern void sys_trace_isr_exit(void);
#endif
static inline void z_arch_isr_direct_footer(int maybe_swap)
static inline void arch_isr_direct_footer(int maybe_swap)
{
#ifdef CONFIG_TRACING
@ -121,7 +121,7 @@ static inline void z_arch_isr_direct_footer(int maybe_swap)
}
}
#define Z_ARCH_ISR_DIRECT_DECLARE(name) \
#define ARCH_ISR_DIRECT_DECLARE(name) \
static inline int name##_body(void); \
__attribute__ ((interrupt ("IRQ"))) void name(void) \
{ \

4
include/arch/arm/misc.h
View file

@ -21,12 +21,12 @@ extern "C" {
#ifndef _ASMLANGUAGE
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}

40
include/arch/arm/syscall.h
View file

@ -36,10 +36,10 @@ extern "C" {
/* Syscall invocation macros. arm-specific machine constraints used to ensure
* args land in the proper registers.
*/
static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -59,10 +59,10 @@ static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -81,9 +81,9 @@ static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -101,9 +101,9 @@ static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -119,8 +119,8 @@ static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r1 __asm__("r1") = arg2;
@ -135,8 +135,8 @@ static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1,
uintptr_t call_id)
{
register u32_t ret __asm__("r0") = arg1;
register u32_t r6 __asm__("r6") = call_id;
@ -149,7 +149,7 @@ static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
{
register u32_t ret __asm__("r0");
register u32_t r6 __asm__("r6") = call_id;
@ -163,7 +163,7 @@ static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
return ret;
}
static inline bool z_arch_is_user_context(void)
static inline bool arch_is_user_context(void)
{
u32_t value;

16
include/arch/nios2/arch.h
View file

@ -38,7 +38,7 @@ extern "C" {
/* There is no notion of priority with the Nios II internal interrupt
* controller and no flags are currently supported.
*/
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
irq_p; \
@ -46,7 +46,7 @@ extern "C" {
extern void z_irq_spurious(void *unused);
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key, tmp;
@ -61,7 +61,7 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
return key;
}
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
/* If the CPU is built without certain features, then
* the only writable bit in the status register is PIE
@ -93,13 +93,13 @@ static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
#endif
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
return key & 1;
}
void z_arch_irq_enable(unsigned int irq);
void z_arch_irq_disable(unsigned int irq);
void arch_irq_enable(unsigned int irq);
void arch_irq_disable(unsigned int irq);
struct __esf {
u32_t ra; /* return address r31 */
@ -173,12 +173,12 @@ enum nios2_exception_cause {
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}

10
include/arch/posix/arch.h
View file

@ -48,28 +48,28 @@ typedef struct __esf z_arch_esf_t;
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
return key == false;
}
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
return posix_irq_lock();
}
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
posix_irq_unlock(key);
}

28
include/arch/riscv/arch.h
View file

@ -64,21 +64,21 @@ extern "C" {
*/
extern u32_t __soc_get_irq(void);
void z_arch_irq_enable(unsigned int irq);
void z_arch_irq_disable(unsigned int irq);
int z_arch_irq_is_enabled(unsigned int irq);
void z_arch_irq_priority_set(unsigned int irq, unsigned int prio);
void arch_irq_enable(unsigned int irq);
void arch_irq_disable(unsigned int irq);
int arch_irq_is_enabled(unsigned int irq);
void arch_irq_priority_set(unsigned int irq, unsigned int prio);
void z_irq_spurious(void *unused);
#if defined(CONFIG_RISCV_HAS_PLIC)
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
z_arch_irq_priority_set(irq_p, priority_p); \
arch_irq_priority_set(irq_p, priority_p); \
irq_p; \
})
#else
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
irq_p; \
@ -89,7 +89,7 @@ void z_irq_spurious(void *unused);
* use atomic instruction csrrc to lock global irq
* csrrc: atomic read and clear bits in CSR register
*/
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key;
ulong_t mstatus;
@ -107,7 +107,7 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
* use atomic instruction csrrs to unlock global irq
* csrrs: atomic read and set bits in CSR register
*/
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
ulong_t mstatus;
@ -117,26 +117,26 @@ static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
: "memory");
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
/* FIXME: looking at z_arch_irq_lock, this should be reducable
/* FIXME: looking at arch_irq_lock, this should be reducable
* to just testing that key is nonzero (because it should only
* have the single bit set). But there is a mask applied to
* the argument in z_arch_irq_unlock() that has me worried
* the argument in arch_irq_unlock() that has me worried
* that something elseswhere might try to set a bit? Do it
* the safe way for now.
*/
return (key & SOC_MSTATUS_IEN) == SOC_MSTATUS_IEN;
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}

12
include/arch/x86/arch.h
View file

@ -18,7 +18,7 @@
#include <arch/x86/mmustructs.h>
#include <arch/x86/thread_stack.h>
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
if ((key & 0x00000200U) != 0U) { /* 'IF' bit */
__asm__ volatile ("sti" ::: "memory");
@ -209,17 +209,17 @@ extern unsigned char _irq_to_interrupt_vector[];
#ifndef _ASMLANGUAGE
extern void z_arch_irq_enable(unsigned int irq);
extern void z_arch_irq_disable(unsigned int irq);
extern void arch_irq_enable(unsigned int irq);
extern void arch_irq_disable(unsigned int irq);
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
return (key & 0x200) != 0;
}
@ -268,7 +268,7 @@ static inline u64_t z_tsc_read(void)
return rv.value;
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}

2
include/arch/x86/arch_inlines.h
View file

@ -15,7 +15,7 @@
#include <arch/x86/intel64/thread.h>
#include <kernel_structs.h>
static inline struct _cpu *z_arch_curr_cpu(void)
static inline struct _cpu *arch_curr_cpu(void)
{
struct _cpu *cpu;

24
include/arch/x86/ia32/arch.h
View file

@ -176,7 +176,7 @@ typedef struct s_isrList {
* 4. z_irq_controller_irq_config() is called at runtime to set the mapping
* between the vector and the IRQ line as well as triggering flags
*/
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
__asm__ __volatile__( \
".pushsection .intList\n\t" \
@ -205,7 +205,7 @@ typedef struct s_isrList {
Z_IRQ_TO_INTERRUPT_VECTOR(irq_p); \
})
#define Z_ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
({ \
NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
@ -215,20 +215,20 @@ typedef struct s_isrList {
#ifdef CONFIG_SYS_POWER_MANAGEMENT
extern void z_arch_irq_direct_pm(void);
#define Z_ARCH_ISR_DIRECT_PM() z_arch_irq_direct_pm()
extern void arch_irq_direct_pm(void);
#define ARCH_ISR_DIRECT_PM() arch_irq_direct_pm()
#else
#define Z_ARCH_ISR_DIRECT_PM() do { } while (false)
#define ARCH_ISR_DIRECT_PM() do { } while (false)
#endif
#define Z_ARCH_ISR_DIRECT_HEADER() z_arch_isr_direct_header()
#define Z_ARCH_ISR_DIRECT_FOOTER(swap) z_arch_isr_direct_footer(swap)
#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
/* FIXME prefer these inline, but see GH-3056 */
extern void z_arch_isr_direct_header(void);
extern void z_arch_isr_direct_footer(int maybe_swap);
extern void arch_isr_direct_header(void);
extern void arch_isr_direct_footer(int maybe_swap);
#define Z_ARCH_ISR_DIRECT_DECLARE(name) \
#define ARCH_ISR_DIRECT_DECLARE(name) \
static inline int name##_body(void); \
__attribute__ ((interrupt)) void name(void *stack_frame) \
{ \
@ -279,7 +279,7 @@ struct _x86_syscall_stack_frame {
u32_t ss;
};
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key;
@ -344,7 +344,7 @@ extern struct task_state_segment _main_tss;
#endif
#if CONFIG_X86_KERNEL_OOPS
#define Z_ARCH_EXCEPT(reason_p) do { \
#define ARCH_EXCEPT(reason_p) do { \
__asm__ volatile( \
"push %[reason]\n\t" \
"int %[vector]\n\t" \

40
include/arch/x86/ia32/syscall.h
View file

@ -34,10 +34,10 @@ extern "C" {
* z_x86_syscall_entry_stub in userspace.S
*/
static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5, uintptr_t arg6,
uintptr_t call_id)
{
u32_t ret;
@ -53,10 +53,10 @@ static inline uintptr_t z_arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t arg5,
uintptr_t call_id)
{
u32_t ret;
@ -68,9 +68,9 @@ static inline uintptr_t z_arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3, uintptr_t arg4,
uintptr_t call_id)
{
u32_t ret;
@ -82,9 +82,9 @@ static inline uintptr_t z_arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
uintptr_t arg3,
uintptr_t call_id)
{
u32_t ret;
@ -95,8 +95,8 @@ static inline uintptr_t z_arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
uintptr_t call_id)
{
u32_t ret;
@ -108,8 +108,8 @@ static inline uintptr_t z_arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1,
uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1,
uintptr_t call_id)
{
u32_t ret;
@ -121,7 +121,7 @@ static inline uintptr_t z_arch_syscall_invoke1(uintptr_t arg1,
return ret;
}
static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
{
u32_t ret;
@ -133,7 +133,7 @@ static inline uintptr_t z_arch_syscall_invoke0(uintptr_t call_id)
return ret;
}
static inline bool z_arch_is_user_context(void)
static inline bool arch_is_user_context(void)
{
int cs;

2
include/arch/x86/ia32/thread.h
View file

@ -202,7 +202,7 @@ typedef struct s_preempFloatReg {
* The thread control structure definition. It contains the
* various fields to manage a _single_ thread. The TCS will be aligned
* to the appropriate architecture specific boundary via the
* z_arch_new_thread() call.
* arch_new_thread() call.
*/
struct _thread_arch {

4
include/arch/x86/intel64/arch.h
View file

@ -18,7 +18,7 @@
#endif
#ifndef _ASMLANGUAGE
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned long key;
@ -64,6 +64,6 @@ typedef struct x86_esf z_arch_esf_t;
* All Intel64 interrupts are dynamically connected.
*/
#define Z_ARCH_IRQ_CONNECT z_arch_irq_connect_dynamic
#define ARCH_IRQ_CONNECT arch_irq_connect_dynamic
#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_ */

26
include/arch/x86/thread_stack.h
View file

@ -195,36 +195,36 @@ struct z_x86_thread_stack_header {
#endif /* CONFIG_USERSPACE */
} __packed __aligned(Z_X86_STACK_BASE_ALIGN);
#define Z_ARCH_THREAD_STACK_RESERVED \
#define ARCH_THREAD_STACK_RESERVED \
((u32_t)sizeof(struct z_x86_thread_stack_header))
#define Z_ARCH_THREAD_STACK_DEFINE(sym, size) \
#define ARCH_THREAD_STACK_DEFINE(sym, size) \
struct _k_thread_stack_element __noinit \
__aligned(Z_X86_STACK_BASE_ALIGN) \
sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
Z_ARCH_THREAD_STACK_RESERVED]
ARCH_THREAD_STACK_RESERVED]
#define Z_ARCH_THREAD_STACK_LEN(size) \
#define ARCH_THREAD_STACK_LEN(size) \
(ROUND_UP((size), \
MAX(Z_X86_STACK_BASE_ALIGN, \
Z_X86_STACK_SIZE_ALIGN)) + \
Z_ARCH_THREAD_STACK_RESERVED)
ARCH_THREAD_STACK_RESERVED)
#define Z_ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
#define ARCH_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) \
struct _k_thread_stack_element __noinit \
__aligned(Z_X86_STACK_BASE_ALIGN) \
sym[nmemb][Z_ARCH_THREAD_STACK_LEN(size)]
sym[nmemb][ARCH_THREAD_STACK_LEN(size)]
#define Z_ARCH_THREAD_STACK_MEMBER(sym, size) \
#define ARCH_THREAD_STACK_MEMBER(sym, size) \
struct _k_thread_stack_element __aligned(Z_X86_STACK_BASE_ALIGN) \
sym[ROUND_UP((size), Z_X86_STACK_SIZE_ALIGN) + \
Z_ARCH_THREAD_STACK_RESERVED]
ARCH_THREAD_STACK_RESERVED]
#define Z_ARCH_THREAD_STACK_SIZEOF(sym) \
(sizeof(sym) - Z_ARCH_THREAD_STACK_RESERVED)
#define ARCH_THREAD_STACK_SIZEOF(sym) \
(sizeof(sym) - ARCH_THREAD_STACK_RESERVED)
#define Z_ARCH_THREAD_STACK_BUFFER(sym) \
((char *)((sym) + Z_ARCH_THREAD_STACK_RESERVED))
#define ARCH_THREAD_STACK_BUFFER(sym) \
((char *)((sym) + ARCH_THREAD_STACK_RESERVED))
#endif /* !_ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_THREAD_STACK_H */

6
include/arch/xtensa/arch.h
View file

@ -40,7 +40,7 @@ extern "C" {
/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
extern void z_irq_priority_set(u32_t irq, u32_t prio, u32_t flags);
#define Z_ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \
Z_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
irq_p; \
@ -53,12 +53,12 @@ extern void z_irq_spurious(void *unused);
extern u32_t z_timer_cycle_get_32(void);
static inline u32_t z_arch_k_cycle_get_32(void)
static inline u32_t arch_k_cycle_get_32(void)
{
return z_timer_cycle_get_32();
}
static ALWAYS_INLINE void z_arch_nop(void)
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}

2
include/arch/xtensa/arch_inlines.h
View file

@ -22,7 +22,7 @@
__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
} while (false)
static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void)
static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
{
_cpu_t *cpu;

18
include/arch/xtensa/irq.h
View file

@ -31,19 +31,19 @@
#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
#endif
#define z_arch_irq_enable(irq) z_soc_irq_enable(irq)
#define z_arch_irq_disable(irq) z_soc_irq_disable(irq)
#define arch_irq_enable(irq) z_soc_irq_enable(irq)
#define arch_irq_disable(irq) z_soc_irq_disable(irq)
#define z_arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq)
#define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq)
#else
#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
#define z_arch_irq_enable(irq) z_xtensa_irq_enable(irq)
#define z_arch_irq_disable(irq) z_xtensa_irq_disable(irq)
#define arch_irq_enable(irq) z_xtensa_irq_enable(irq)
#define arch_irq_disable(irq) z_xtensa_irq_disable(irq)
#define z_arch_irq_is_enabled(irq) z_xtensa_irq_is_enabled(irq)
#define arch_irq_is_enabled(irq) z_xtensa_irq_is_enabled(irq)
#endif
@ -57,18 +57,18 @@ static ALWAYS_INLINE void z_xtensa_irq_disable(u32_t irq)
z_xt_ints_off(1 << irq);
}
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
{
unsigned int key = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
return key;
}
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
{
XTOS_RESTORE_INTLEVEL(key);
}
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
{
return (key & 0xf) == 0; /* INTLEVEL field */
}