From 4f6b48ee6cf44edd1a91b89e8008ac21e26fc05f Mon Sep 17 00:00:00 2001 From: Appana Durga Kedareswara rao Date: Sat, 29 Mar 2025 20:00:10 +0530 Subject: [PATCH] soc: amd: Add support for AMD Versal Gen 2 RPU Add support for the RPU, real-time processing unit on Versal Gen 2 SoC. It is based on Cortext-R52 processor. The patch contains initial wiring and configuration for generic board with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global timer and UART. versal2.dtsi contains common peripherals integrated into Versal Gen 2 SoC, and versal2_r52.dtsi has peripherals which are private to Cortex-R52 processor. Signed-off-by: Appana Durga Kedareswara rao --- dts/arm/xilinx/versal2_r52.dtsi | 49 ++++++++++++++++++++++++++++++ dts/vendor/amd/versal2.dtsi | 32 +++++++++++++++++++ soc/xlnx/versal2/CMakeLists.txt | 19 ++++++++++++ soc/xlnx/versal2/Kconfig | 15 +++++++++ soc/xlnx/versal2/Kconfig.defconfig | 21 +++++++++++++ soc/xlnx/versal2/Kconfig.soc | 20 ++++++++++++ soc/xlnx/versal2/arm_mpu_regions.c | 39 ++++++++++++++++++++++++ soc/xlnx/versal2/soc.c | 28 +++++++++++++++++ soc/xlnx/versal2/soc.h | 14 +++++++++ soc/xlnx/versal2/soc.yml | 4 +++ 10 files changed, 241 insertions(+) create mode 100644 dts/arm/xilinx/versal2_r52.dtsi create mode 100644 dts/vendor/amd/versal2.dtsi create mode 100644 soc/xlnx/versal2/CMakeLists.txt create mode 100644 soc/xlnx/versal2/Kconfig create mode 100644 soc/xlnx/versal2/Kconfig.defconfig create mode 100644 soc/xlnx/versal2/Kconfig.soc create mode 100644 soc/xlnx/versal2/arm_mpu_regions.c create mode 100644 soc/xlnx/versal2/soc.c create mode 100644 soc/xlnx/versal2/soc.h create mode 100644 soc/xlnx/versal2/soc.yml diff --git a/dts/arm/xilinx/versal2_r52.dtsi b/dts/arm/xilinx/versal2_r52.dtsi new file mode 100644 index 00000000000..4166b809d23 --- /dev/null +++ b/dts/arm/xilinx/versal2_r52.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Versal Gen 2 RPU"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <0>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + status = "okay"; + }; +}; + +&soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@e2000000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0xe2000000 0x10000>, <0xe2100000 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; +}; diff --git a/dts/vendor/amd/versal2.dtsi b/dts/vendor/amd/versal2.dtsi new file mode 100644 index 00000000000..e5ab51ad59f --- /dev/null +++ b/dts/vendor/amd/versal2.dtsi @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2025, Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + soc: soc { + ocm: memory@bbf00000 { + compatible = "zephyr,memory-region"; + reg = <0xbbf00000 DT_SIZE_M(1)>; + status = "disabled"; + zephyr,memory-region = "OCM"; + }; + + uart0: uart@f1920000 { + compatible = "arm,sbsa-uart"; + reg = <0xf1920000 0x4c>; + status = "disabled"; + interrupt-names = "irq_0"; + interrupts = ; + }; + + uart1: uart@f1930000 { + compatible = "arm,sbsa-uart"; + reg = <0xf1930000 0x1000>; + status = "disabled"; + interrupt-names = "irq_1"; + interrupts = ; + }; + }; +}; diff --git a/soc/xlnx/versal2/CMakeLists.txt b/soc/xlnx/versal2/CMakeLists.txt new file mode 100644 index 00000000000..ecf12267ace --- /dev/null +++ b/soc/xlnx/versal2/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c +) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + arm_mpu_regions.c +) + +zephyr_include_directories(.) + +if(CONFIG_SOC_AMD_VERSAL2_RPU) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/xlnx/versal2/Kconfig b/soc/xlnx/versal2/Kconfig new file mode 100644 index 00000000000..dbc60f57303 --- /dev/null +++ b/soc/xlnx/versal2/Kconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_AMD_VERSAL2_RPU + select ARM + select ARM_ARCH_TIMER + select CPU_CORTEX_R52 + select SOC_EARLY_INIT_HOOK + select CPU_HAS_DCLS + select GIC_SINGLE_SECURITY_STATE + select CPU_HAS_ARM_MPU + select ARM_MPU diff --git a/soc/xlnx/versal2/Kconfig.defconfig b/soc/xlnx/versal2/Kconfig.defconfig new file mode 100644 index 00000000000..8b177f49985 --- /dev/null +++ b/soc/xlnx/versal2/Kconfig.defconfig @@ -0,0 +1,21 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_AMD_VERSAL2 + +if SOC_AMD_VERSAL2_RPU + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + default 256 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +endif # SOC_AMD_VERSAL2_RPU + +endif # SOC_VERSAL2_AMD diff --git a/soc/xlnx/versal2/Kconfig.soc b/soc/xlnx/versal2/Kconfig.soc new file mode 100644 index 00000000000..6482c63bfa7 --- /dev/null +++ b/soc/xlnx/versal2/Kconfig.soc @@ -0,0 +1,20 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_AMD_VERSAL2 + bool + +config SOC_AMD_VERSAL2_RPU + bool + select SOC_AMD_VERSAL2 + help + AMD Versal Gen 2 RPU + +config SOC_FAMILY + default "amd_versal2" if SOC_AMD_VERSAL2 + +config SOC + default "amd_versal2_rpu" if SOC_AMD_VERSAL2_RPU diff --git a/soc/xlnx/versal2/arm_mpu_regions.c b/soc/xlnx/versal2/arm_mpu_regions.c new file mode 100644 index 00000000000..865452c6e38 --- /dev/null +++ b/soc/xlnx/versal2/arm_mpu_regions.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#define DEVICE_REGION_START 0xE2000000U +#define DEVICE_REGION_END 0xF8000000U + +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY("vector", + (uintptr_t)_vector_start, + REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)), + + MPU_REGION_ENTRY("SRAM_TEXT", + (uintptr_t)__text_region_start, + REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)), + + MPU_REGION_ENTRY("SRAM_RODATA", + (uintptr_t)__rodata_region_start, + REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)), + + MPU_REGION_ENTRY("SRAM_DATA", + (uintptr_t)__rom_region_end, + REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)), + + MPU_REGION_ENTRY("DEVICE", + DEVICE_REGION_START, + REGION_DEVICE_ATTR(DEVICE_REGION_END)), +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/xlnx/versal2/soc.c b/soc/xlnx/versal2/soc.c new file mode 100644 index 00000000000..3b269b4eefc --- /dev/null +++ b/soc/xlnx/versal2/soc.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +void soc_early_init_hook(void) +{ + if (IS_ENABLED(CONFIG_ICACHE)) { + if (!(__get_SCTLR() & SCTLR_I_Msk)) { + L1C_InvalidateICacheAll(); + __set_SCTLR(__get_SCTLR() | SCTLR_I_Msk); + barrier_isync_fence_full(); + } + } + + if (IS_ENABLED(CONFIG_DCACHE)) { + if (!(__get_SCTLR() & SCTLR_C_Msk)) { + L1C_InvalidateDCacheAll(); + __set_SCTLR(__get_SCTLR() | SCTLR_C_Msk); + barrier_dsync_fence_full(); + } + } +} diff --git a/soc/xlnx/versal2/soc.h b/soc/xlnx/versal2/soc.h new file mode 100644 index 00000000000..e2e4ce9ea10 --- /dev/null +++ b/soc/xlnx/versal2/soc.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_XLNX_VERSAL2_SOC_H_ +#define _SOC_XLNX_VERSAL2_SOC_H_ + +/* Define CMSIS configurations */ +#define __GIC_PRESENT 0 +#define __TIM_PRESENT 0 + +#endif /* _SOC_XLNX_VERSAL2_SOC_H_ */ diff --git a/soc/xlnx/versal2/soc.yml b/soc/xlnx/versal2/soc.yml new file mode 100644 index 00000000000..1c3f2d4575f --- /dev/null +++ b/soc/xlnx/versal2/soc.yml @@ -0,0 +1,4 @@ +family: +- name: amd_versal2 + socs: + - name: amd_versal2_rpu