drivers: serial: xlnx_ps: drop usage of uart_device_config
Create a driver specific configuration structure, containing the required fields only. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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1 changed files with 28 additions and 26 deletions
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@ -133,7 +133,11 @@
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/** Device configuration structure */
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struct uart_xlnx_ps_dev_config {
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struct uart_device_config uconf;
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uint32_t reg;
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uint32_t sys_clk_freq;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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uint32_t baud_rate;
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};
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@ -225,7 +229,7 @@ static void set_baudrate(const struct device *dev, uint32_t baud_rate)
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uint32_t reg_base;
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baud = dev_cfg->baud_rate;
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clk_freq = dev_cfg->uconf.sys_clk_freq;
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clk_freq = dev_cfg->sys_clk_freq;
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/* Calculate divisor and baud rate generator value */
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if ((baud != 0) && (clk_freq != 0)) {
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@ -260,7 +264,7 @@ static void set_baudrate(const struct device *dev, uint32_t baud_rate)
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* be changed safely at this time.
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*/
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET);
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sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET);
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}
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@ -281,7 +285,7 @@ static int uart_xlnx_ps_init(const struct device *dev)
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uint32_t reg_val;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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/* Disable RX/TX before changing any configuration data */
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xlnx_ps_disable_uart(reg_base);
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@ -309,7 +313,7 @@ static int uart_xlnx_ps_init(const struct device *dev)
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sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_ISR_OFFSET);
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/* Attach to & unmask the corresponding interrupt vector */
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dev_cfg->uconf.irq_config_func(dev);
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dev_cfg->irq_config_func(dev);
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#endif
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@ -332,7 +336,7 @@ static int uart_xlnx_ps_poll_in(const struct device *dev, unsigned char *c)
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uint32_t reg_val;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
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if ((reg_val & XUARTPS_SR_RXEMPTY) == 0) {
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*c = (unsigned char)sys_read32(reg_base +
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@ -363,7 +367,7 @@ static void uart_xlnx_ps_poll_out(const struct device *dev, unsigned char c)
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uint32_t reg_val;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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/* wait for transmitter to ready to accept a character */
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do {
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reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
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@ -593,7 +597,7 @@ static int uart_xlnx_ps_configure(const struct device *dev,
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struct uart_xlnx_ps_dev_config *dev_cfg =
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(struct uart_xlnx_ps_dev_config *)dev->config;
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uint32_t reg_base = dev_cfg->uconf.regs;
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uint32_t reg_base = dev_cfg->reg;
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uint32_t mode_reg = 0;
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uint32_t modemcr_reg = 0;
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@ -806,7 +810,7 @@ static int uart_xlnx_ps_config_get(const struct device *dev,
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* Control register).
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*/
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uint32_t reg_base = dev_cfg->uconf.regs;
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uint32_t reg_base = dev_cfg->reg;
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uint32_t mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET);
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uint32_t modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);
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@ -836,7 +840,7 @@ static int uart_xlnx_ps_fifo_fill(const struct device *dev,
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int size)
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{
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base = dev_cfg->uconf.regs;
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uint32_t reg_base = dev_cfg->reg;
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uint32_t data_iter = 0;
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sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IDR_OFFSET);
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@ -867,7 +871,7 @@ static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data,
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uint32_t reg_base;
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int inum = 0;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
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while (inum < size && (reg_val & XUARTPS_SR_RXEMPTY) == 0) {
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@ -890,7 +894,7 @@ static void uart_xlnx_ps_irq_tx_enable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(
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(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),
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reg_base + XUARTPS_IER_OFFSET);
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@ -906,7 +910,7 @@ static void uart_xlnx_ps_irq_tx_disable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(
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(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),
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reg_base + XUARTPS_IDR_OFFSET);
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@ -922,7 +926,7 @@ static void uart_xlnx_ps_irq_tx_disable(const struct device *dev)
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static int uart_xlnx_ps_irq_tx_ready(const struct device *dev)
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{
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base = dev_cfg->uconf.regs;
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uint32_t reg_base = dev_cfg->reg;
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uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
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if ((reg_val & (XUARTPS_SR_TTRIG | XUARTPS_SR_TXEMPTY)) == 0) {
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@ -945,7 +949,7 @@ static int uart_xlnx_ps_irq_tx_complete(const struct device *dev)
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uint32_t reg_base;
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uint32_t reg_val;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
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if ((reg_val & XUARTPS_SR_TXEMPTY) == 0) {
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return 0;
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@ -964,7 +968,7 @@ static void uart_xlnx_ps_irq_rx_enable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IER_OFFSET);
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}
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@ -978,7 +982,7 @@ static void uart_xlnx_ps_irq_rx_disable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IDR_OFFSET);
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}
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@ -992,7 +996,7 @@ static void uart_xlnx_ps_irq_rx_disable(const struct device *dev)
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static int uart_xlnx_ps_irq_rx_ready(const struct device *dev)
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{
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base = dev_cfg->uconf.regs;
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uint32_t reg_base = dev_cfg->reg;
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uint32_t reg_val = sys_read32(reg_base + XUARTPS_ISR_OFFSET);
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if ((reg_val & XUARTPS_IXR_RTRIG) == 0) {
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@ -1013,7 +1017,7 @@ static void uart_xlnx_ps_irq_err_enable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(
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XUARTPS_IXR_TOVR /* [12] Transmitter FIFO Overflow */
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| XUARTPS_IXR_TOUT /* [8] Receiver Timerout */
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@ -1035,7 +1039,7 @@ static void uart_xlnx_ps_irq_err_disable(const struct device *dev)
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const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
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uint32_t reg_base;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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sys_write32(
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XUARTPS_IXR_TOVR /* [12] Transmitter FIFO Overflow */
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| XUARTPS_IXR_TOUT /* [8] Receiver Timerout */
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@ -1059,7 +1063,7 @@ static int uart_xlnx_ps_irq_is_pending(const struct device *dev)
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uint32_t reg_imr;
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uint32_t reg_isr;
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reg_base = dev_cfg->uconf.regs;
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reg_base = dev_cfg->reg;
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reg_imr = sys_read32(reg_base + XUARTPS_IMR_OFFSET);
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reg_isr = sys_read32(reg_base + XUARTPS_ISR_OFFSET);
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@ -1168,12 +1172,10 @@ static struct uart_xlnx_ps_dev_data_t uart_xlnx_ps_dev_data_##port
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#define UART_XLNX_PS_DEV_CFG(port) \
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static struct uart_xlnx_ps_dev_config uart_xlnx_ps_dev_cfg_##port = { \
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.uconf = { \
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.regs = DT_INST_REG_ADDR(port), \
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.sys_clk_freq = DT_INST_PROP(port, clock_frequency), \
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UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \
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}, \
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.reg = DT_INST_REG_ADDR(port), \
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.sys_clk_freq = DT_INST_PROP(port, clock_frequency), \
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.baud_rate = DT_INST_PROP(port, current_speed), \
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UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \
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}
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#define UART_XLNX_PS_INIT(port) \
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