drivers: adc: stm32: add support for stm32g0 series
Adds support for ADC on G0 series. Simple implementation: sequencer not fully configurable, and only one common sampling time. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger
Maureen Helm
parent
56c3c8b2e3
commit
4ed375040e
2 changed files with 64 additions and 12 deletions
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@ -29,6 +29,7 @@ LOG_MODULE_REGISTER(adc_stm32);
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#include <pinmux/stm32/pinmux_stm32.h>
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32G0X) && \
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!defined(CONFIG_SOC_SERIES_STM32L0X)
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#define RANK(n) LL_ADC_REG_RANK_##n
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static const uint32_t table_rank[] = {
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@ -148,7 +149,8 @@ static const uint32_t table_samp_time[] = {
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SMP_TIME(239, S_5),
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};
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#endif /* ADC5_V1_1 */
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#elif defined(CONFIG_SOC_SERIES_STM32L0X)
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#elif defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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static const uint16_t acq_time_tbl[8] = {2, 4, 8, 13, 20, 40, 80, 161};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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@ -211,7 +213,9 @@ struct adc_stm32_data {
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uint8_t resolution;
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uint8_t channel_count;
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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int8_t acq_time_index;
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#endif
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};
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@ -256,6 +260,7 @@ static void adc_stm32_start_conversion(const struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_ADC_REG_StartConversion(adc);
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@ -332,6 +337,11 @@ static int start_read(const struct device *dev,
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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/* STM32G0 in "not fully configurable" sequencer mode */
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LL_ADC_REG_SetSequencerChannels(adc, channel);
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while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
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}
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#else
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LL_ADC_REG_SetSequencerRanks(adc, table_rank[0], channel);
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LL_ADC_REG_SetSequencerLength(adc, table_seq_len[0]);
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@ -343,7 +353,21 @@ static int start_read(const struct device *dev,
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return err;
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}
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#if !defined(CONFIG_SOC_SERIES_STM32F1X)
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#if defined(CONFIG_SOC_SERIES_STM32G0X)
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/*
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* Errata: Writing ADC_CFGR1 register while ADEN bit is set
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* resets RES[1:0] bitfield. We need to disable and enable adc.
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*/
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if (LL_ADC_IsEnabled(adc) == 1UL) {
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LL_ADC_Disable(adc);
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}
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while (LL_ADC_IsEnabled(adc) == 1UL) {
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}
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LL_ADC_SetResolution(adc, resolution);
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LL_ADC_Enable(adc);
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while (LL_ADC_IsActiveFlag_ADRDY(adc) != 1UL) {
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}
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#elif !defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_ADC_SetResolution(adc, resolution);
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#endif
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@ -352,6 +376,7 @@ static int start_read(const struct device *dev,
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_ADC_EnableIT_EOC(adc);
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@ -457,6 +482,9 @@ static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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table_samp_time[acq_time_index]);
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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LL_ADC_SetSamplingTimeCommonChannels(adc, LL_ADC_SAMPLINGTIME_COMMON_1,
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table_samp_time[acq_time_index]);
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#else
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LL_ADC_SetChannelSamplingTime(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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@ -467,7 +495,9 @@ static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
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static int adc_stm32_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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struct adc_stm32_data *data = dev->data;
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#endif
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int acq_time_index;
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@ -482,7 +512,9 @@ static int adc_stm32_channel_setup(const struct device *dev,
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if (acq_time_index < 0) {
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return acq_time_index;
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}
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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if (data->acq_time_index == -1) {
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data->acq_time_index = acq_time_index;
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} else {
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@ -533,6 +565,7 @@ static void adc_stm32_calib(const struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32G4X)
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LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
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#elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_StartCalibration(adc);
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#elif defined(CONFIG_SOC_SERIES_STM32H7X)
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@ -555,12 +588,15 @@ static int adc_stm32_init(const struct device *dev)
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LOG_DBG("Initializing....");
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data->dev = dev;
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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/*
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* All conversion time for all channels on one ADC instance for F0 and
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* L0 series chips has to be the same. This additional variable is for
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* checking if the conversion time selection of all channels on one ADC
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* instance is the same.
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* L0 series chips has to be the same. For STM32G0 currently only one
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* of the two available common channel conversion times is used.
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* This additional variable is for checking if the conversion time
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* selection of all channels on one ADC instance is the same.
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*/
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data->acq_time_index = -1;
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#endif
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@ -591,12 +627,13 @@ static int adc_stm32_init(const struct device *dev)
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LL_ADC_DisableDeepPowerDown(adc);
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#endif
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/*
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* F3, L4, WB and G4 ADC modules need some time to be stabilized before
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* performing any enable or calibration actions.
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* F3, L4, WB, G0 and G4 ADC modules need some time
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* to be stabilized before performing any enable or calibration actions.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_ADC_EnableInternalRegulator(adc);
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@ -609,6 +646,7 @@ static int adc_stm32_init(const struct device *dev)
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#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
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@ -634,6 +672,7 @@ static int adc_stm32_init(const struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
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@ -653,6 +692,7 @@ static int adc_stm32_init(const struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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/*
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@ -677,10 +717,11 @@ static int adc_stm32_init(const struct device *dev)
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X)
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/*
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* Enabling ADC modules in L4, WB and G4 series may fail if they are
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* Enabling ADC modules in L4, WB, G0 and G4 series may fail if they are
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* still not stabilized, this will wait for a short time to ensure ADC
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* modules are properly enabled.
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*/
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@ -230,6 +230,17 @@
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status = "disabled";
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label = "SPI_2";
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};
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adc1: adc@40012400 {
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compatible = "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <12 0>;
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interrupt-names = "combined";
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status = "disabled";
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label = "ADC_1";
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#io-channel-cells = <1>;
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};
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};
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};
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