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arc: move disabling/invalidation of caches earlier

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Too much code might run with a stale icache, before _PrepC(), so move
the invalidation/disabling code earlier. The asm code does the exact
same thing disable_icache() and invalidate_dcache() were doing.

Change-Id: If52f4e4a1de546fb82873c91ead95614a44b106d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit is contained in:
Benjamin Walsh 2016-11-29 17:09:31 -05:00 • committed by Anas Nashif
commit 4e8a54c1e3
2 changed files with 29 additions and 3 deletions
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6
arch/arc/core/prep_c.c
View file

@ -34,6 +34,8 @@
#include <nano_internal.h>
/* XXX - keep for future use in full-featured cache APIs */
#if 0
/**
*
* @brief Disable the i-cache if present
@ -79,7 +81,7 @@ static void invalidate_dcache(void)
}
_arc_v2_aux_reg_write(_ARC_V2_DC_IVDC, 1);
}
#endif
/**
*
@ -121,8 +123,6 @@ extern FUNC_NORETURN void _Cstart(void);
void _PrepC(void)
{
disable_icache();
invalidate_dcache();
adjust_vector_table_base();
_bss_zero();
_data_copy();

26
arch/arc/core/reset.S
View file

@ -73,6 +73,32 @@ SECTION_FUNC(TEXT,__start)
/* lock interrupts: will get unlocked when switch to main task */
clri
mov r1, 1
invalidate_and_disable_icache:
lr r0, [_ARC_V2_I_CACHE_BUILD]
and.f r0, r0, 0xff
bz.nd invalidate_dcache
mov_s r2, 0
sr r2, [_ARC_V2_IC_IVIC]
/* writing to IC_IVIC needs 3 NOPs */
nop
nop
nop
sr r1, [_ARC_V2_IC_CTRL]
invalidate_dcache:
lr r3, [_ARC_V2_D_CACHE_BUILD]
and.f r3, r3, 0xff
bz.nd done_cache_invalidate
sr r1, [_ARC_V2_DC_IVDC]
done_cache_invalidate:
#ifdef CONFIG_INIT_STACKS
/*
* use the main stack to call memset on the interrupt stack and the