sam: adc: Updated SAM ADC driver.
Updated to work with new ADC API. Signed-off-by: Justin Watson <jwatson5@gmail.com>
This commit is contained in:
parent
c68e41dffe
commit
4e551aabb6
6 changed files with 338 additions and 178 deletions
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@ -95,10 +95,12 @@
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#define CONFIG_ADC_0_IRQ ATMEL_SAM_AFEC_4003C000_IRQ_0
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#define CONFIG_ADC_0_IRQ_PRI ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY
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#define CONFIG_ADC_0_NAME ATMEL_SAM_AFEC_4003C000_LABEL
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#define CONFIG_ADC_0_PERIPHERAL_ID ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID
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#define CONFIG_ADC_1_BASE_ADDRESS ATMEL_SAM_AFEC_40064000_BASE_ADDRESS
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#define CONFIG_ADC_1_IRQ ATMEL_SAM_AFEC_40064000_IRQ_0
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#define CONFIG_ADC_1_IRQ_PRI ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY
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#define CONFIG_ADC_1_NAME ATMEL_SAM_AFEC_40064000_LABEL
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#define CONFIG_ADC_1_PERIPHERAL_ID ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID
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/* End of SoC Level DTS fixup file */
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@ -56,6 +56,8 @@ features:
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| ADC | on-chip | ADC via AFEC |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by Zephyr.
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@ -7,3 +7,4 @@ toolchain:
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- gnuarmemb
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supported:
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- netif:eth
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- adc
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@ -1,11 +1,15 @@
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/*
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* Copyright (c) 2017 comsuisse AG
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* Copyright (c) 2018 Justin Watson
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM MCU family ADC (AFEC) driver.
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*
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* This is an implementation of the Zephyr ADC driver using the SAM Analog
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* Front-End Controller (AFEC) peripheral.
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*/
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#include <errno.h>
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@ -16,143 +20,254 @@
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#include <soc.h>
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#include <adc.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define SYS_LOG_DOMAIN "dev/adc_sam_afec"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_ADC_LEVEL
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#include <logging/sys_log.h>
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#define ADC_CHANNELS 12
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struct adc_sam_dev_cfg {
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Afec *regs;
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const struct soc_gpio_pin *pin_trigger;
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void (*irq_config)(void);
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u8_t irq_id;
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u8_t periph_id;
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};
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struct channel_samples {
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u16_t *buffer;
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u32_t length;
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};
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struct adc_sam_dev_data {
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struct k_sem sem_meas;
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struct k_sem mutex_thread;
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u16_t active_channels;
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u16_t measured_channels;
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u16_t active_chan_last;
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struct channel_samples samples[ADC_CHANNELS];
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};
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#define NUM_CHANNELS 12
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#define CONF_ADC_PRESCALER ((SOC_ATMEL_SAM_MCK_FREQ_HZ / 15000000) - 1)
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#define DEV_NAME(dev) ((dev)->config->name)
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typedef void (*cfg_func_t)(struct device *dev);
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struct adc_sam_data {
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struct adc_context ctx;
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struct device *dev;
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/* Pointer to the buffer in the sequence. */
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u16_t *buffer;
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/* Pointer to the beginning of a sample. Consider the number of
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* channels in the sequence: this buffer changes by that amount
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* so all the channels would get repeated.
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*/
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u16_t *repeat_buffer;
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/* Bit mask of the channels to be sampled. */
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u32_t channels;
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/* Index of the channel being sampled. */
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u8_t channel_id;
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};
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struct adc_sam_cfg {
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Afec *regs;
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cfg_func_t cfg_func;
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u32_t periph_id;
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struct soc_gpio_pin afec_trg_pin;
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};
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#define DEV_CFG(dev) \
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((const struct adc_sam_dev_cfg *const)(dev)->config->config_info)
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((const struct adc_sam_cfg *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct adc_sam_dev_data *const)(dev)->driver_data)
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((struct adc_sam_data *)(dev)->driver_data)
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static void adc_sam_isr(void *arg)
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static int adc_sam_channel_setup(struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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struct device *dev = (struct device *)arg;
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const struct adc_sam_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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Afec *const afec = dev_cfg->regs;
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struct channel_samples *samples = dev_data->samples;
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u32_t isr_status;
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u16_t value;
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const struct adc_sam_cfg * const cfg = DEV_CFG(dev);
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Afec *const afec = cfg->regs;
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isr_status = afec->AFEC_ISR;
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for (int i = 0; i < ADC_CHANNELS; i++) {
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if (isr_status & BIT(i)) {
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/* Channel i has been sampled */
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afec->AFEC_CSELR = AFEC_CSELR_CSEL(i);
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value = (u16_t)(afec->AFEC_CDR);
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u8_t channel_id = channel_cfg->channel_id;
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if (samples[i].length > 0) {
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/* Save sample */
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*samples[i].buffer = value;
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samples[i].length--;
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samples[i].buffer++;
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/* Clear the gain bits for the channel. */
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afec->AFEC_CGR &= ~(3 << channel_id * 2);
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dev_data->measured_channels |= BIT(i);
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}
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if (samples[i].length == 0) {
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afec->AFEC_CHDR |= BIT(i);
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afec->AFEC_IDR |= BIT(i);
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dev_data->active_channels &= ~BIT(i);
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}
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}
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switch (channel_cfg->gain) {
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case ADC_GAIN_1:
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/* A value of 0 in this register is a gain of 1. */
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break;
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case ADC_GAIN_1_2:
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afec->AFEC_CGR |= (1 << (channel_id * 2));
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break;
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case ADC_GAIN_1_4:
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afec->AFEC_CGR |= (2 << (channel_id * 2));
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break;
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default:
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SYS_LOG_ERR("Selected ADC gain is not valid");
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return -EINVAL;
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}
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if (dev_data->active_chan_last == dev_data->measured_channels) {
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if (!dev_data->active_channels) {
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/* No more conversions needed */
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k_sem_give(&dev_data->sem_meas);
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} else {
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/* Start another conversion with remaining channels */
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dev_data->measured_channels = 0;
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dev_data->active_chan_last = dev_data->active_channels;
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afec->AFEC_CR = AFEC_CR_START;
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}
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}
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}
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static int adc_sam_read(struct device *dev, struct adc_seq_table *seq_tbl)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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Afec *const afec = dev_cfg->regs;
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u8_t channel;
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u32_t num_samples;
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k_sem_take(&dev_data->mutex_thread, K_FOREVER);
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dev_data->active_channels = 0;
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/* Enable chosen channels */
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for (int i = 0; i < seq_tbl->num_entries; i++) {
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channel = seq_tbl->entries[i].channel_id;
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if (channel >= ADC_CHANNELS) {
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return -EINVAL;
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}
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/* Check and set number of requested samples */
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num_samples = seq_tbl->entries[i].buffer_length / sizeof(u16_t);
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if (!num_samples) {
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return -EINVAL;
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}
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dev_data->samples[channel].length = num_samples;
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/* Set start of sample buffer */
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dev_data->samples[channel].buffer =
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(u16_t *)seq_tbl->entries[i].buffer;
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/* Enable channel */
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dev_data->active_channels |= BIT(channel);
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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SYS_LOG_ERR("Selected ADC acquisition time is not valid");
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return -EINVAL;
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}
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/* Enable chosen channels and their interrupts */
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afec->AFEC_CHER = dev_data->active_channels;
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afec->AFEC_IER = dev_data->active_channels;
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if (channel_cfg->reference != ADC_REF_EXTERNAL0) {
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SYS_LOG_ERR("Selected reference is not valid");
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return -EINVAL;
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}
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/* Start conversions */
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dev_data->measured_channels = 0;
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dev_data->active_chan_last = dev_data->active_channels;
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afec->AFEC_CR = AFEC_CR_START;
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k_sem_take(&dev_data->sem_meas, K_FOREVER);
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if (channel_cfg->differential) {
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SYS_LOG_ERR("Differential input is not supported");
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return -EINVAL;
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}
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k_sem_give(&dev_data->mutex_thread);
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/* Set single ended channels to unsigned and differential channels
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* to signed conversions.
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*/
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afec->AFEC_EMR &= ~(AFEC_EMR_SIGNMODE(
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AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val));
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return 0;
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}
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static void adc_sam_configure(struct device *dev)
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static void adc_sam_start_conversion(struct device *dev)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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Afec *const afec = dev_cfg->regs;
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const struct adc_sam_cfg *const cfg = DEV_CFG(dev);
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struct adc_sam_data *data = DEV_DATA(dev);
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Afec *const afec = cfg->regs;
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/* Reset the AFEC */
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data->channel_id = find_lsb_set(data->channels) - 1;
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SYS_LOG_DBG("Starting channel %d", data->channel_id);
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/* Disable all channels. */
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afec->AFEC_CHDR = 0xfff;
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afec->AFEC_IDR = 0xfff;
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/* Enable the ADC channel. This also enables/selects the channel pin as
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* an input to the AFEC (50.5.1 SAM E70 datasheet).
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*/
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afec->AFEC_CHER = (1 << data->channel_id);
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/* Enable the interrupt for the channel. */
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afec->AFEC_IER = (1 << data->channel_id);
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/* Start the conversions. */
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afec->AFEC_CR = AFEC_CR_START;
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}
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/**
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* This is only called once at the beginning of all the conversions,
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* all channels as a group.
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*/
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_sam_data *data = CONTAINER_OF(ctx, struct adc_sam_data, ctx);
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data->channels = ctx->sequence->channels;
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adc_sam_start_conversion(data->dev);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_sam_data *data = CONTAINER_OF(ctx, struct adc_sam_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int check_buffer_size(const struct adc_sequence *sequence,
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u8_t active_channels)
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{
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size_t needed_buffer_size;
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needed_buffer_size = active_channels * sizeof(u16_t);
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if (sequence->options) {
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needed_buffer_size *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed_buffer_size) {
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SYS_LOG_ERR("Provided buffer is too small (%u/%u)",
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sequence->buffer_size, needed_buffer_size);
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return -ENOMEM;
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}
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return 0;
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}
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static int start_read(struct device *dev, const struct adc_sequence *sequence)
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{
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struct adc_sam_data *data = DEV_DATA(dev);
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int error = 0;
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u32_t channels = sequence->channels;
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data->channels = 0;
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/* Signal an error if the channel selection is invalid (no channels or
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* a non-existing one is selected).
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*/
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if (channels == 0 ||
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(channels & (~0UL << NUM_CHANNELS))) {
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SYS_LOG_ERR("Invalid selection of channels");
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return -EINVAL;
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}
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if (sequence->oversampling != 0) {
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SYS_LOG_ERR("Oversampling is not supported");
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return -EINVAL;
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}
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if (sequence->resolution != 12) {
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/* TODO JKW: Support the Enhanced Resolution Mode 50.6.3 page
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* 1544.
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*/
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SYS_LOG_ERR("ADC resolution value %d is not valid",
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sequence->resolution);
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return -EINVAL;
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}
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if (sequence->options->interval_us != 0) {
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SYS_LOG_ERR("Spaced intervals not supported");
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return -EINVAL;
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}
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u8_t num_active_channels = 0;
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u8_t channel = 0;
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while (channels > 0) {
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if (channels & 1) {
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++num_active_channels;
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}
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channels >>= 1;
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++channel;
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}
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error = check_buffer_size(sequence, num_active_channels);
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if (error) {
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return error;
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}
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/* In the context you have a pointer to the adc_sam_data structure
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* only.
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*/
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data->buffer = sequence->buffer;
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data->repeat_buffer = sequence->buffer;
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/* At this point we allow the scheduler to do other things while
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* we wait for the conversions to complete. This is provided by the
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* adc_context functions. However, the caller of this function is
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* blocked until the results are in.
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*/
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int adc_sam_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_sam_data *data = DEV_DATA(dev);
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adc_context_lock(&data->ctx, false, NULL);
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return start_read(dev, sequence);
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}
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static int adc_sam_init(struct device *dev)
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{
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const struct adc_sam_cfg *const cfg = DEV_CFG(dev);
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struct adc_sam_data *data = DEV_DATA(dev);
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Afec *const afec = cfg->regs;
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/* Reset the AFEC. */
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afec->AFEC_CR = AFEC_CR_SWRST;
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afec->AFEC_MR = AFEC_MR_TRGEN_DIS
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@ -164,100 +279,127 @@ static void adc_sam_configure(struct device *dev)
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| AFEC_MR_ONE
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| AFEC_MR_USEQ_NUM_ORDER;
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/* Set all channels CM voltage to Vrefp/2 (512) */
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for (int i = 0; i < ADC_CHANNELS; i++) {
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/* Set all channels CM voltage to Vrefp/2 (512). */
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for (int i = 0; i < NUM_CHANNELS; i++) {
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afec->AFEC_CSELR = i;
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afec->AFEC_COCR = 512;
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}
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/* Enable PGA and Current Bias */
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/* Enable PGA and Current Bias. */
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afec->AFEC_ACR = AFEC_ACR_PGA0EN
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| AFEC_ACR_PGA1EN
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| AFEC_ACR_IBCTL(1);
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}
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static int adc_sam_initialize(struct device *dev)
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{
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const struct adc_sam_dev_cfg *dev_cfg = DEV_CFG(dev);
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struct adc_sam_dev_data *const dev_data = DEV_DATA(dev);
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soc_pmc_peripheral_enable(cfg->periph_id);
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/* Initialize semaphores */
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k_sem_init(&dev_data->sem_meas, 0, 1);
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k_sem_init(&dev_data->mutex_thread, 1, 1);
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cfg->cfg_func(dev);
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/* Configure interrupts */
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dev_cfg->irq_config();
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data->dev = dev;
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/* Enable module's clock */
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soc_pmc_peripheral_enable(dev_cfg->periph_id);
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/* Configure ADC */
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adc_sam_configure(dev);
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/* Enable module interrupt */
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irq_enable(dev_cfg->irq_id);
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SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api adc_sam_driver_api = {
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.read = adc_sam_read,
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#ifdef CONFIG_ADC_ASYNC
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static int adc_sam_read_async(struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_sam_data *data = DEV_DATA(dev);
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adc_context_lock(&data->ctx, true, async);
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return start_read(dev, sequence);
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}
|
||||
#endif
|
||||
|
||||
static const struct adc_driver_api adc_sam_api = {
|
||||
.channel_setup = adc_sam_channel_setup,
|
||||
.read = adc_sam_read,
|
||||
#ifdef CONFIG_ADC_ASYNC
|
||||
.read_async = adc_sam_read_async,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* ADC_0 */
|
||||
static void adc_sam_isr(void *arg)
|
||||
{
|
||||
struct device *dev = (struct device *)arg;
|
||||
struct adc_sam_data *data = DEV_DATA(dev);
|
||||
const struct adc_sam_cfg *const cfg = DEV_CFG(dev);
|
||||
Afec *const afec = cfg->regs;
|
||||
u16_t result;
|
||||
|
||||
afec->AFEC_CHDR |= BIT(data->channel_id);
|
||||
afec->AFEC_IDR |= BIT(data->channel_id);
|
||||
|
||||
afec->AFEC_CSELR = AFEC_CSELR_CSEL(data->channel_id);
|
||||
result = (u16_t)(afec->AFEC_CDR);
|
||||
|
||||
*data->buffer++ = result;
|
||||
data->channels &= ~BIT(data->channel_id);
|
||||
|
||||
if (data->channels) {
|
||||
adc_sam_start_conversion(dev);
|
||||
} else {
|
||||
/* Called once all conversions have completed.*/
|
||||
adc_context_on_sampling_done(&data->ctx, dev);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ADC_0
|
||||
static struct device DEVICE_NAME_GET(adc0_sam);
|
||||
static void adc0_sam_cfg_func(struct device *dev);
|
||||
|
||||
static void adc0_irq_config(void)
|
||||
{
|
||||
IRQ_CONNECT(AFEC0_IRQn, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr,
|
||||
DEVICE_GET(adc0_sam), 0);
|
||||
}
|
||||
|
||||
static const struct soc_gpio_pin pin_adc0 = PIN_AFE0_ADTRG;
|
||||
|
||||
static const struct adc_sam_dev_cfg adc0_sam_config = {
|
||||
.regs = AFEC0,
|
||||
.pin_trigger = &pin_adc0,
|
||||
.periph_id = ID_AFEC0,
|
||||
.irq_config = adc0_irq_config,
|
||||
.irq_id = AFEC0_IRQn,
|
||||
static const struct adc_sam_cfg adc0_sam_cfg = {
|
||||
.regs = (Afec *)CONFIG_ADC_0_BASE_ADDRESS,
|
||||
.cfg_func = adc0_sam_cfg_func,
|
||||
.periph_id = CONFIG_ADC_0_PERIPHERAL_ID,
|
||||
.afec_trg_pin = PIN_AFE0_ADTRG,
|
||||
};
|
||||
|
||||
static struct adc_sam_dev_data adc0_sam_data;
|
||||
static struct adc_sam_data adc0_sam_data = {
|
||||
ADC_CONTEXT_INIT_TIMER(adc0_sam_data, ctx),
|
||||
ADC_CONTEXT_INIT_LOCK(adc0_sam_data, ctx),
|
||||
ADC_CONTEXT_INIT_SYNC(adc0_sam_data, ctx),
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(adc0_sam, CONFIG_ADC_0_NAME, &adc_sam_initialize,
|
||||
&adc0_sam_data, &adc0_sam_config, POST_KERNEL,
|
||||
CONFIG_ADC_INIT_PRIORITY, &adc_sam_driver_api);
|
||||
#endif
|
||||
DEVICE_AND_API_INIT(adc0_sam, CONFIG_ADC_0_NAME, adc_sam_init,
|
||||
&adc0_sam_data, &adc0_sam_cfg, POST_KERNEL,
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &adc_sam_api);
|
||||
|
||||
/* ADC_1 */
|
||||
static void adc0_sam_cfg_func(struct device *dev)
|
||||
{
|
||||
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr,
|
||||
DEVICE_GET(adc0_sam), 0);
|
||||
irq_enable(CONFIG_ADC_0_IRQ);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC_0 */
|
||||
|
||||
#ifdef CONFIG_ADC_1
|
||||
static struct device DEVICE_NAME_GET(adc1_sam);
|
||||
static void adc1_sam_cfg_func(struct device *dev);
|
||||
|
||||
static void adc1_irq_config(void)
|
||||
{
|
||||
IRQ_CONNECT(AFEC1_IRQn, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr,
|
||||
DEVICE_GET(adc1_sam), 0);
|
||||
}
|
||||
|
||||
static const struct soc_gpio_pin pin_adc1 = PIN_AFE1_ADTRG;
|
||||
|
||||
static const struct adc_sam_dev_cfg adc1_sam_config = {
|
||||
.regs = AFEC1,
|
||||
.pin_trigger = &pin_adc1,
|
||||
.periph_id = ID_AFEC1,
|
||||
.irq_config = adc1_irq_config,
|
||||
.irq_id = AFEC1_IRQn,
|
||||
static const struct adc_sam_cfg adc1_sam_cfg = {
|
||||
.regs = (Afec *)CONFIG_ADC_1_BASE_ADDRESS,
|
||||
.cfg_func = adc1_sam_cfg_func,
|
||||
.periph_id = CONFIG_ADC_1_PERIPHERAL_ID,
|
||||
.afec_trg_pin = PIN_AFE1_ADTRG,
|
||||
};
|
||||
|
||||
static struct adc_sam_dev_data adc1_sam_data;
|
||||
static struct adc_sam_data adc1_sam_data = {
|
||||
ADC_CONTEXT_INIT_TIMER(adc1_sam_data, ctx),
|
||||
ADC_CONTEXT_INIT_LOCK(adc1_sam_data, ctx),
|
||||
ADC_CONTEXT_INIT_SYNC(adc1_sam_data, ctx),
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(adc1_sam, CONFIG_ADC_1_NAME, &adc_sam_initialize,
|
||||
&adc1_sam_data, &adc1_sam_config, POST_KERNEL,
|
||||
CONFIG_ADC_INIT_PRIORITY, &adc_sam_driver_api);
|
||||
#endif
|
||||
DEVICE_AND_API_INIT(adc1_sam, CONFIG_ADC_1_NAME, adc_sam_init,
|
||||
&adc1_sam_data, &adc1_sam_cfg, POST_KERNEL,
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &adc_sam_api);
|
||||
|
||||
static void adc1_sam_cfg_func(struct device *dev)
|
||||
{
|
||||
IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr,
|
||||
DEVICE_GET(adc1_sam), 0);
|
||||
irq_enable(CONFIG_ADC_1_IRQ);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC_1 */
|
||||
|
|
3
tests/drivers/adc/adc_api/boards/sam_e70_xplained.conf
Normal file
3
tests/drivers/adc/adc_api/boards/sam_e70_xplained.conf
Normal file
|
@ -0,0 +1,3 @@
|
|||
CONFIG_ADC=y
|
||||
CONFIG_ADC_SAM_AFEC=y
|
||||
CONFIG_ADC_0=y
|
|
@ -94,6 +94,16 @@
|
|||
#define ADC_1ST_CHANNEL_ID 1
|
||||
#define ADC_1ST_CHANNEL_INPUT 0
|
||||
|
||||
#elif defined(CONFIG_BOARD_SAM_E70_XPLAINED)
|
||||
|
||||
#define ADC_DEVICE_NAME CONFIG_ADC_0_NAME
|
||||
#define ADC_RESOLUTION 12
|
||||
#define ADC_GAIN ADC_GAIN_1
|
||||
#define ADC_REFERENCE ADC_REF_EXTERNAL0
|
||||
#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
|
||||
#define ADC_1ST_CHANNEL_ID 0
|
||||
#define ADC_1ST_CHANNEL_INPUT 0
|
||||
|
||||
#else
|
||||
#error "Unsupported board."
|
||||
#endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue