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soc: nxp_rw: Update pinctrl setting for FlexSPI

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The FSEL bit for FlexSPI should not be cleared as part of
configuring the FlexSPI pins.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2024-07-23 13:59:25 -05:00 • committed by Benjamin Cabé
commit 4e31be313a
1 changed files with 0 additions and 7 deletions
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7
soc/nxp/rw/pinctrl_defs.h
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@ -284,49 +284,42 @@
#define IOMUX_GPIO_CLR_28 \ #define IOMUX_GPIO_CLR_28 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_29 \ #define IOMUX_GPIO_CLR_29 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_30 \ #define IOMUX_GPIO_CLR_30 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_31 \ #define IOMUX_GPIO_CLR_31 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_32 \ #define IOMUX_GPIO_CLR_32 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_33 \ #define IOMUX_GPIO_CLR_33 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
#define IOMUX_GPIO_CLR_34 \ #define IOMUX_GPIO_CLR_34 \
(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */