drivers: hwinfo: add reset cause support for iMX RT series

Add a shim driver to get/clear the reset reason on NXP i.MX
RT controllers

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>

drivers/hwinfo/CMakeLists.txt

@@ -12,6 +12,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_IMXRT       hwinfo_imxrt.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX       hwinfo_litex.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM    hwinfo_mcux_rcm.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM    hwinfo_mcux_sim.c)
+zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC    hwinfo_mcux_src.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SYSCON hwinfo_mcux_syscon.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF         hwinfo_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6       hwinfo_psoc6.c)

drivers/hwinfo/Kconfig

@@ -49,6 +49,13 @@ config HWINFO_MCUX_SIM
 	help
 	  Enable NXP kinetis mcux SIM hwinfo driver.
 
+config HWINFO_MCUX_SRC
+	bool "NXP SRC reset cause"
+	default y
+	depends on HAS_MCUX_SRC
+	help
+	  Enable NXP i.MX mcux SRC hwinfo driver.
+
 config HWINFO_MCUX_SYSCON
 	bool "NXP LPC device ID"
 	default y

drivers/hwinfo/hwinfo_mcux_src.c

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2021 Basalte bv
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_imx_src
+
+#include <soc.h>
+#include <drivers/hwinfo.h>
+#include <string.h>
+#include <sys/byteorder.h>
+
+#include <fsl_src.h>
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "No nxp,imx-src compatible device found");
+
+int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
+{
+	uint32_t flags = 0;
+
+	uint32_t reason = SRC_GetResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0));
+
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && \
+	FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
+	if (reason & kSRC_IppResetPinFlag) {
+		flags |= RESET_PIN;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
+	if (reason & kSRC_PowerOnResetFlag) {
+		flags |= RESET_POR;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP)
+	if (reason & kSRC_CoreLockupResetFlag) {
+		flags |= RESET_CPU_LOCKUP;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
+	if (reason & kSRC_CsuResetFlag) {
+		flags |= RESET_SECURITY;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
+	if (reason & kSRC_SNVSFailResetFlag) {
+		flags |= RESET_HARDWARE;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && \
+	FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
+	if (reason & kSRC_IppUserResetFlag) {
+		flags |= RESET_USER;
+	}
+#endif
+	if (reason & kSRC_WatchdogResetFlag) {
+		flags |= RESET_WATCHDOG;
+	}
+	if (reason & kSRC_JTAGGeneratedResetFlag) {
+		flags |= RESET_DEBUG;
+	}
+	if (reason & kSRC_JTAGSoftwareResetFlag) {
+		flags |= RESET_DEBUG;
+	}
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST)
+	if (reason & kSRC_JTAGSystemResetFlag) {
+		flags |= RESET_DEBUG;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
+	if (reason & kSRC_SoftwareResetFlag) {
+		flags |= RESET_SOFTWARE;
+	}
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
+	if (reason & kSRC_Wdog3ResetFlag) {
+		flags |= RESET_WATCHDOG;
+	}
+#endif
+	if (reason & kSRC_TemperatureSensorResetFlag) {
+		flags |= RESET_TEMPERATURE;
+	}
+#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
+	if (reason & kSRC_WarmBootIndicationFlag) {
+		flags |= RESET_SOFTWARE;
+	}
+#endif
+
+	*cause = flags;
+
+	return 0;
+}
+
+int z_impl_hwinfo_clear_reset_cause(void)
+{
+	uint32_t reason = -1;
+
+	SRC_ClearResetStatusFlags((SRC_Type *)DT_INST_REG_ADDR(0), reason);
+
+	return 0;
+}
+
+int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
+{
+	*supported = (RESET_WATCHDOG
+		      | RESET_DEBUG
+		      | RESET_TEMPERATURE
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && \
+		      FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
+		      | RESET_PIN
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
+		      | RESET_POR
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST)
+		      | RESET_CPU_LOCKUP
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
+		      | RESET_SECURITY
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
+		      | RESET_HARDWARE
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && \
+		      FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
+		      | RESET_USER
+#endif
+#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
+		      | RESET_SOFTWARE
+#endif
+		      );
+
+	return 0;
+}

dts/arm/nxp/nxp_rt.dtsi

@@ -529,6 +529,13 @@
 			};
 		};
 
+		src: reset-controller@400f8000 {
+			compatible = "nxp,imx-src";
+			reg = <0x400f8000 0x4000>;
+			status = "okay";
+			label = "SRC";
+		};
+
 		trng: random@400cc000 {
 			compatible = "nxp,kinetis-trng";
 			reg = <0x400cc000 0x4000>;

modules/Kconfig.mcux

@@ -171,6 +171,12 @@ config HAS_MCUX_SIM
 	  Set if the system integration module (SIM) module is present in the
 	  SoC.
 
+config HAS_MCUX_SRC
+	bool
+	help
+	  Set if the system reset controller (SRC) module is present in the
+	  SoC.
+
 config HAS_MCUX_TRNG
 	bool
 	help