drivers: display_nrf_led_matrix: Add option to light LEDs in groups
Add a new DT property named "pixel-group-size" that allows users to configure the driver to refresh the matrix by illuminating multiple LEDs in particular rows simultaneously. This way the maximum possible brightness of the LEDs can be increased (as they can be lit longer) and the timer interrupt handler is executed less frequently, what results in decreased CPU load, but more GPIOTE/PPI channels needs to be allocated if the PWM peripheral cannot be used. Thus, it is left to users to select the configuration that suits them best. Update definitions of both the bbc_microbit boards with this new property, using the maximum available group size (to achieve maximum possible brightness). For v2, no new resources are used (only all channels in the already used PWM peripheral are now utilized). For v1, two more GPIOTE and PPI channels are allocated. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek
Carles Cufí
parent
2f4fbc7621
commit
4dfab40cac
5 changed files with 221 additions and 87 deletions
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@ -11,12 +11,12 @@ config DISPLAY_NRF_LED_MATRIX
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default $(dt_compat_enabled,$(DT_COMPAT_NRF_LED_MATRIX))
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help
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Enable driver for a LED matrix with rows and columns driven by
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GPIOs. The matrix is refreshed pixel by pixel (only one LED is
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turned on in particular time slots) and each pixel can have one
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of 256 levels of brightness (0 means off completely).
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GPIOs. The driver allows setting one of 256 levels of brightness
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(where 0 means off completely) for each of the LEDs independently.
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Assignment of GPIOs to rows and columns and the mapping of those
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to pixels are specified in properties of a "nordic,nrf-led-matrix"
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compatible node in devicetree.
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The driver uses one TIMER instance and, depending on what is set
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in devicetree, one PWM instance or one PPI channel and one GPIOTE
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channel.
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The driver uses one TIMER instance and, depending on what is set in
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devicetree, one PWM instance or one or more GPIOTE and PPI channels
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(the latter value depends on the chosen pixel group size - the number
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of LEDs in one row that can be lit simultaneously).
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@ -15,25 +15,48 @@
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#ifdef PPI_PRESENT
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#include <nrfx_ppi.h>
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#endif
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#include <nrf_peripherals.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(nrf_led_matrix, CONFIG_DISPLAY_LOG_LEVEL);
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#define MATRIX_NODE DT_INST(0, nordic_nrf_led_matrix)
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#define TIMER_NODE DT_PHANDLE(MATRIX_NODE, timer)
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#define USE_PWM DT_NODE_HAS_PROP(MATRIX_NODE, pwm)
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#define PWM_NODE DT_PHANDLE(MATRIX_NODE, pwm)
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#define ROW_COUNT DT_PROP_LEN(MATRIX_NODE, row_gpios)
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#define COL_COUNT DT_PROP_LEN(MATRIX_NODE, col_gpios)
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#define GROUP_SIZE DT_PROP(MATRIX_NODE, pixel_group_size)
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#if (GROUP_SIZE > DT_PROP(TIMER_NODE, cc_num) - 1) || \
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(USE_PWM && GROUP_SIZE > PWM0_CH_NUM)
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#error "Invalid pixel-group-size configured."
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#endif
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#define X_PIXELS DT_PROP(MATRIX_NODE, width)
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#define Y_PIXELS DT_PROP(MATRIX_NODE, height)
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#define PIXEL_COUNT DT_PROP_LEN(MATRIX_NODE, pixel_mapping)
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BUILD_ASSERT(PIXEL_COUNT == (X_PIXELS * Y_PIXELS),
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"Invalid length of pixel-mapping");
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#if (PIXEL_COUNT != (X_PIXELS * Y_PIXELS))
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#error "Invalid length of pixel-mapping."
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#endif
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#define PIXEL_MAPPING(idx) DT_PROP_BY_IDX(MATRIX_NODE, pixel_mapping, idx)
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#define GET_DT_ROW_IDX(pixel_idx) \
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_GET_ROW_IDX(PIXEL_MAPPING(pixel_idx))
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#define GET_ROW_IDX(dev_config, pixel_idx) \
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_GET_ROW_IDX(dev_config->pixel_mapping[pixel_idx])
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#define _GET_ROW_IDX(byte) (byte >> 4)
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#define GET_DT_COL_IDX(pixel_idx) \
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_GET_COL_IDX(PIXEL_MAPPING(pixel_idx))
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#define GET_COL_IDX(dev_config, pixel_idx) \
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_GET_COL_IDX(dev_config->pixel_mapping[pixel_idx])
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#define _GET_COL_IDX(byte) (byte & 0xF)
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#define CHECK_PIXEL(node_id, pha, idx) \
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BUILD_ASSERT((PIXEL_MAPPING(idx) >> 4) < ROW_COUNT, \
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"Invalid row index in pixel-mapping["#idx"]"); \
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BUILD_ASSERT((PIXEL_MAPPING(idx) & 0xF) < COL_COUNT, \
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"Invalid column index in pixel-mapping["#idx"]");
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BUILD_ASSERT(GET_DT_ROW_IDX(idx) < ROW_COUNT, \
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"Invalid row index in pixel-mapping["#idx"]."); \
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BUILD_ASSERT(GET_DT_COL_IDX(idx) < COL_COUNT, \
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"Invalid column index in pixel-mapping["#idx"].");
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DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping, CHECK_PIXEL)
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#define REFRESH_FREQUENCY DT_PROP(MATRIX_NODE, refresh_frequency)
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@ -42,17 +65,23 @@ DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping, CHECK_PIXEL)
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#define PWM_CLK_CONFIG NRF_PWM_CLK_16MHz
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#define BRIGHTNESS_MAX 255
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#define QUANTUM (BASE_FREQUENCY / (REFRESH_FREQUENCY * PIXEL_COUNT * \
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BRIGHTNESS_MAX))
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#define QUANTUM (BASE_FREQUENCY / (REFRESH_FREQUENCY * BRIGHTNESS_MAX * \
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PIXEL_COUNT * GROUP_SIZE))
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#define PIXEL_PERIOD (BRIGHTNESS_MAX * QUANTUM)
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BUILD_ASSERT(PIXEL_PERIOD <= BIT_MASK(16));
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#if USE_PWM
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BUILD_ASSERT(PIXEL_PERIOD <= PWM_COUNTERTOP_COUNTERTOP_Msk);
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#if (PIXEL_PERIOD > BIT_MASK(16)) || \
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(USE_PWM && PIXEL_PERIOD > PWM_COUNTERTOP_COUNTERTOP_Msk)
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#error "Invalid pixel period. Change refresh-frequency or pixel-group-size."
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#endif
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#define ACTIVE_LOW_MASK 0x80
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#define PSEL_MASK 0x7F
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#if (GROUP_SIZE > 1)
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#define ITERATION_COUNT ROW_COUNT * COL_COUNT
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#else
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#define ITERATION_COUNT PIXEL_COUNT
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#endif
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struct display_drv_config {
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NRF_TIMER_Type *timer;
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#if USE_PWM
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@ -61,16 +90,20 @@ struct display_drv_config {
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uint8_t rows[ROW_COUNT];
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uint8_t cols[COL_COUNT];
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uint8_t pixel_mapping[PIXEL_COUNT];
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#if (GROUP_SIZE > 1)
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uint8_t refresh_order[ITERATION_COUNT];
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#endif
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};
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struct display_drv_data {
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#if USE_PWM
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uint16_t seq;
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uint16_t seq[PWM0_CH_NUM];
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#else
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uint8_t gpiote_ch;
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uint8_t gpiote_ch[GROUP_SIZE];
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#endif
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uint8_t pixel_idx;
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uint8_t framebuf[PIXEL_COUNT];
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uint8_t iteration;
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uint8_t prev_row_idx;
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uint8_t brightness;
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bool blanking;
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};
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@ -111,7 +144,7 @@ static int api_blanking_off(const struct device *dev)
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const struct display_drv_config *dev_config = dev->config;
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if (dev_data->blanking) {
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dev_data->pixel_idx = PIXEL_COUNT - 1;
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dev_data->iteration = ITERATION_COUNT - 1;
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_CLEAR);
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
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@ -264,57 +297,32 @@ const struct display_driver_api driver_api = {
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.set_orientation = api_set_orientation,
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};
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static void timer_irq_handler(void *arg)
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static void prepare_pixel_pulse(const struct device *dev,
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uint8_t pixel_idx,
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uint8_t channel_idx)
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{
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const struct device *dev = arg;
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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uint8_t prev_row_idx, pixel_mapping, row_pin_info, col_pin_info;
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uint16_t pulse;
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/* The timer is automagically stopped and cleared by shortcuts
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* on the same event (COMPARE0) that generates this interrupt.
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* But the event itself needs to be cleared here.
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*/
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nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
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uint8_t col_idx = GET_COL_IDX(dev_config, pixel_idx);
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uint8_t col_pin_info = dev_config->cols[col_idx];
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uint8_t col_psel = (col_pin_info & PSEL_MASK);
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bool col_active_low = (col_pin_info & ACTIVE_LOW_MASK);
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uint16_t pulse = dev_data->framebuf[pixel_idx] * QUANTUM;
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/* Disable the row that contains the previously handled pixel. */
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prev_row_idx = dev_config->pixel_mapping[dev_data->pixel_idx] >> 4;
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set_pin(dev_config->rows[prev_row_idx], false);
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/* Disconnect that pixel column pin from the peripheral driving it. */
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#if USE_PWM
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nrf_pwm_disable(dev_config->pwm);
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#else
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch] = 0;
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#endif
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/* Switch to the next pixel. */
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++dev_data->pixel_idx;
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if (dev_data->pixel_idx >= PIXEL_COUNT) {
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dev_data->pixel_idx = 0;
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}
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pixel_mapping = dev_config->pixel_mapping[dev_data->pixel_idx];
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row_pin_info = dev_config->rows[pixel_mapping >> 4];
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col_pin_info = dev_config->cols[pixel_mapping & 0xF];
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/* Prepare the low pulse on the column pin for the current pixel. */
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pulse = dev_data->framebuf[dev_data->pixel_idx] * QUANTUM;
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#if USE_PWM
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dev_config->pwm->PSEL.OUT[0] = col_pin_info & PSEL_MASK;
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dev_data->seq = pulse
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| ((col_pin_info & ACTIVE_LOW_MASK) ? 0 : BIT(15));
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nrf_pwm_enable(dev_config->pwm);
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nrf_pwm_task_trigger(dev_config->pwm, NRF_PWM_TASK_SEQSTART0);
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dev_config->pwm->PSEL.OUT[channel_idx] = col_psel;
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dev_data->seq[channel_idx] = pulse | (col_active_low ? 0 : BIT(15));
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#else
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uint32_t gpiote_cfg = GPIOTE_CONFIG_MODE_Task
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| ((col_pin_info & PSEL_MASK) << GPIOTE_CONFIG_PSEL_Pos);
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| (col_psel << GPIOTE_CONFIG_PSEL_Pos);
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if (col_pin_info & ACTIVE_LOW_MASK) {
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if (col_active_low) {
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gpiote_cfg |= (GPIOTE_CONFIG_POLARITY_LoToHi
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<< GPIOTE_CONFIG_POLARITY_Pos)
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/* If there should be no pulse at all for a given
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* pixel, its column GPIO needs to be configured
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* as initially inactive.
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/* If there should be no pulse at all for
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* a given pixel, its column GPIO needs
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* to be configured as initially inactive.
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*/
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| ((pulse == 0 ? GPIOTE_CONFIG_OUTINIT_High
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: GPIOTE_CONFIG_OUTINIT_Low)
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@ -326,12 +334,90 @@ static void timer_irq_handler(void *arg)
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: GPIOTE_CONFIG_OUTINIT_High)
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<< GPIOTE_CONFIG_OUTINIT_Pos);
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}
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nrf_timer_cc_set(dev_config->timer, 1, pulse);
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch] = gpiote_cfg;
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/* First timer channel is used for timing the period of pulses. */
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nrf_timer_cc_set(dev_config->timer, 1 + channel_idx, pulse);
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch[channel_idx]] = gpiote_cfg;
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#endif /* USE_PWM */
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}
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static void timer_irq_handler(void *arg)
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{
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const struct device *dev = arg;
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struct display_drv_data *dev_data = dev->data;
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const struct display_drv_config *dev_config = dev->config;
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uint8_t iteration = dev_data->iteration;
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uint8_t pixel_idx;
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uint8_t row_idx;
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/* The timer is automagically stopped and cleared by shortcuts
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* on the same event (COMPARE0) that generates this interrupt.
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* But the event itself needs to be cleared here.
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*/
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nrf_timer_event_clear(dev_config->timer, NRF_TIMER_EVENT_COMPARE0);
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/* Disable the row that was enabled in the previous iteration. */
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set_pin(dev_config->rows[dev_data->prev_row_idx], false);
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/* Disconnect used column pins from the peripheral that drove them. */
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#if USE_PWM
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nrf_pwm_disable(dev_config->pwm);
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for (int i = 0; i < GROUP_SIZE; ++i) {
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dev_config->pwm->PSEL.OUT[i] = NRF_PWM_PIN_NOT_CONNECTED;
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}
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#else
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for (int i = 0; i < GROUP_SIZE; ++i) {
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NRF_GPIOTE->CONFIG[dev_data->gpiote_ch[i]] = 0;
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}
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#endif
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/* Enable the row drive for the current pixel and restart the timer. */
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set_pin(row_pin_info, true);
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for (int i = 0; i < GROUP_SIZE; ++i) {
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#if (GROUP_SIZE > 1)
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do {
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++iteration;
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if (iteration >= ITERATION_COUNT) {
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iteration = 0;
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}
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pixel_idx = dev_config->refresh_order[iteration];
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} while (pixel_idx >= PIXEL_COUNT);
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#else
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++iteration;
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if (iteration >= ITERATION_COUNT) {
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iteration = 0;
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}
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pixel_idx = iteration;
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#endif /* (GROUP_SIZE > 1) */
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if (i == 0) {
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row_idx = GET_ROW_IDX(dev_config, pixel_idx);
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} else {
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/* If the next pixel is in a different row, it cannot
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* be lit within this group.
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*/
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if (row_idx != GET_ROW_IDX(dev_config, pixel_idx)) {
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break;
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}
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}
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dev_data->iteration = iteration;
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prepare_pixel_pulse(dev, pixel_idx, i);
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}
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/* Enable the row drive for the current pixel. */
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set_pin(dev_config->rows[row_idx], true);
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dev_data->prev_row_idx = row_idx;
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#if USE_PWM
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/* Now that all the channels are configured, the PWM can be started. */
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nrf_pwm_enable(dev_config->pwm);
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nrf_pwm_task_trigger(dev_config->pwm, NRF_PWM_TASK_SEQSTART0);
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#endif
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/* Restart the timer. */
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nrf_timer_task_trigger(dev_config->timer, NRF_TIMER_TASK_START);
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}
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@ -348,15 +434,15 @@ static int instance_init(const struct device *dev)
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NRF_PWM_PIN_NOT_CONNECTED,
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};
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nrf_pwm_sequence_t sequence = {
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.values.p_raw = &dev_data->seq,
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.length = 1,
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.values.p_raw = dev_data->seq,
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.length = PWM0_CH_NUM,
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};
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nrf_pwm_pins_set(dev_config->pwm, out_psels);
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nrf_pwm_configure(dev_config->pwm,
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PWM_CLK_CONFIG, NRF_PWM_MODE_UP, PIXEL_PERIOD);
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nrf_pwm_decoder_set(dev_config->pwm,
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NRF_PWM_LOAD_COMMON, NRF_PWM_STEP_TRIGGERED);
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NRF_PWM_LOAD_INDIVIDUAL, NRF_PWM_STEP_TRIGGERED);
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nrf_pwm_sequence_set(dev_config->pwm, 0, &sequence);
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nrf_pwm_loop_set(dev_config->pwm, 0);
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nrf_pwm_shorts_set(dev_config->pwm, NRF_PWM_SHORT_SEQEND0_STOP_MASK);
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@ -364,23 +450,36 @@ static int instance_init(const struct device *dev)
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nrfx_err_t err;
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nrf_ppi_channel_t ppi_ch;
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err = nrfx_ppi_channel_alloc(&ppi_ch);
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if (err != NRFX_SUCCESS) {
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return -ENOMEM;
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}
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for (int i = 0; i < GROUP_SIZE; ++i) {
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uint8_t *gpiote_ch = &dev_data->gpiote_ch[i];
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err = nrfx_gpiote_channel_alloc(&dev_data->gpiote_ch);
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if (err != NRFX_SUCCESS) {
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nrfx_ppi_channel_free(ppi_ch);
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return -ENOMEM;
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}
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err = nrfx_ppi_channel_alloc(&ppi_ch);
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if (err != NRFX_SUCCESS) {
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LOG_ERR("Failed to allocate PPI channel.");
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/* Do not bother with freeing resources allocated
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* so far. The application needs to be reconfigured
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* anyway.
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*/
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return -ENOMEM;
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}
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nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
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nrf_timer_event_address_get(dev_config->timer,
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nrf_timer_compare_event_get(1)),
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nrf_gpiote_event_address_get(NRF_GPIOTE,
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nrf_gpiote_out_task_get(dev_data->gpiote_ch)));
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nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
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err = nrfx_gpiote_channel_alloc(gpiote_ch);
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if (err != NRFX_SUCCESS) {
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LOG_ERR("Failed to allocate GPIOTE channel.");
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/* Do not bother with freeing resources allocated
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* so far. The application needs to be reconfigured
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* anyway.
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*/
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return -ENOMEM;
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}
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nrf_ppi_channel_endpoint_setup(NRF_PPI, ppi_ch,
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nrf_timer_event_address_get(dev_config->timer,
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nrf_timer_compare_event_get(1 + i)),
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nrf_gpiote_event_address_get(NRF_GPIOTE,
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nrf_gpiote_out_task_get(*gpiote_ch)));
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nrf_ppi_channel_enable(NRF_PPI, ppi_ch);
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}
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#endif /* USE_PWM */
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for (uint8_t i = 0; i < ROW_COUNT; ++i) {
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@ -391,7 +490,7 @@ static int instance_init(const struct device *dev)
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NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_DISCONNECT,
|
||||
NRF_GPIO_PIN_NOPULL,
|
||||
NRF_GPIO_PIN_S0S1,
|
||||
NRF_GPIO_PIN_H0H1,
|
||||
NRF_GPIO_PIN_NOSENSE);
|
||||
}
|
||||
|
||||
|
|
@ -434,14 +533,30 @@ static struct display_drv_data instance_data = {
|
|||
((DT_GPIO_FLAGS_BY_IDX(node_id, pha, idx) & GPIO_ACTIVE_LOW) ? \
|
||||
ACTIVE_LOW_MASK : 0)),
|
||||
|
||||
#define ADD_FF(i, _) 0xFF,
|
||||
#define FILL_ROW_WITH_FF(node_id, pha, idx) UTIL_LISTIFY(COL_COUNT, ADD_FF)
|
||||
#define GET_PIXEL_ORDINAL(node_id, pha, idx) \
|
||||
[GET_DT_ROW_IDX(idx) * COL_COUNT + \
|
||||
GET_DT_COL_IDX(idx)] = idx,
|
||||
|
||||
static const struct display_drv_config instance_config = {
|
||||
.timer = (NRF_TIMER_Type *)DT_REG_ADDR(TIMER_NODE),
|
||||
#if USE_PWM
|
||||
.pwm = (NRF_PWM_Type *)DT_REG_ADDR(DT_PHANDLE(MATRIX_NODE, pwm)),
|
||||
.pwm = (NRF_PWM_Type *)DT_REG_ADDR(PWM_NODE),
|
||||
#endif
|
||||
.rows = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios, GET_PIN_INFO) },
|
||||
.cols = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, col_gpios, GET_PIN_INFO) },
|
||||
.pixel_mapping = DT_PROP(MATRIX_NODE, pixel_mapping),
|
||||
#if (GROUP_SIZE > 1)
|
||||
/* The whole array is by default filled with FFs, then the elements
|
||||
* for the actually used row/columns pairs are overwritten (using
|
||||
* designators) with the proper ordinal values for pixels.
|
||||
*/
|
||||
.refresh_order = { DT_FOREACH_PROP_ELEM(MATRIX_NODE, row_gpios,
|
||||
FILL_ROW_WITH_FF)
|
||||
DT_FOREACH_PROP_ELEM(MATRIX_NODE, pixel_mapping,
|
||||
GET_PIXEL_ORDINAL) },
|
||||
#endif
|
||||
};
|
||||
|
||||
DEVICE_DT_DEFINE(MATRIX_NODE,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue