diff --git a/soc/intel/intel_adsp/ace/ace-link.ld b/soc/intel/intel_adsp/ace/ace-link.ld
index aa92a212ea0..55090118042 100644
--- a/soc/intel/intel_adsp/ace/ace-link.ld
+++ b/soc/intel/intel_adsp/ace/ace-link.ld
@@ -170,7 +170,9 @@ SECTIONS {
    * .text.
    */
   .imrdata : ALIGN(4096) {
+    __imr_data_start = .;
     *(.imrdata .imrdata.*)
+    __imr_data_end = .;
   } >imr
 
   /* Cold code in IMR memory */
diff --git a/soc/intel/intel_adsp/ace/mmu_ace30.c b/soc/intel/intel_adsp/ace/mmu_ace30.c
index ed233ddf862..29a8818cafb 100644
--- a/soc/intel/intel_adsp/ace/mmu_ace30.c
+++ b/soc/intel/intel_adsp/ace/mmu_ace30.c
@@ -21,6 +21,8 @@ extern char __common_ram_region_start[];
 extern char __common_ram_region_end[];
 extern char __cold_start[];
 extern char __cold_end[];
+extern char __imr_data_start[];
+extern char __imr_data_end[];
 extern char __coldrodata_start[];
 
 
@@ -133,6 +135,12 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 		.end   = (uint32_t)_imr_end,
 		.name = "imr coldrodata",
 	},
+	{
+		.start = (uint32_t)__imr_data_start,
+		.end   = (uint32_t)__imr_data_end,
+		.attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB,
+		.name = "imr data",
+	},
 	{
 		.start = (uint32_t)IMR_L3_HEAP_BASE,
 		.end   = (uint32_t)(IMR_L3_HEAP_BASE + IMR_L3_HEAP_SIZE),