soc: nordic: Remove support for nRF54H20 EngA
This was a preview revision of the SoC that will no longer be supported. Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
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7 changed files with 0 additions and 99 deletions
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@ -1,12 +1,6 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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CPU_PATH := $(dt_nodelabel_path,cpu)
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CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH))
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config RV_BOOT_HART
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default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR
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config RISCV_MCAUSE_EXCEPTION_MASK
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config RISCV_MCAUSE_EXCEPTION_MASK
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default 0xFFF
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default 0xFFF
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@ -32,31 +32,6 @@ config SOC_NRF54H20_CPURAD
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config SOC_NRF54H20_CPUPPR
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config SOC_NRF54H20_CPUPPR
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depends on RISCV_CORE_NORDIC_VPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54H20_ENGA_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select CPU_HAS_FPU
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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config SOC_NRF54H20_ENGA_CPURAD
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_DCACHE
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select CPU_HAS_ICACHE
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select CPU_HAS_FPU
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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config SOC_NRF54H20_ENGA_CPUPPR
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depends on RISCV_CORE_NORDIC_VPR
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if SOC_NRF54H20
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if SOC_NRF54H20
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config NRF_ENABLE_ICACHE
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config NRF_ENABLE_ICACHE
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@ -1,14 +0,0 @@
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# Nordic Semiconductor nRF54H20 Application MCU
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_ENGA_CPUAPP
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config NUM_IRQS
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default 471
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config NRF_REGTOOL_GENERATE_UICR
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default y
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endif # SOC_NRF54H20_ENGA_CPUAPP
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@ -1,12 +0,0 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_ENGA_CPUPPR
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config NUM_IRQS
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default 496
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config SYS_CLOCK_TICKS_PER_SEC
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default 1000
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endif # SOC_NRF54H20_ENGA_CPUPPR
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@ -1,14 +0,0 @@
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# Nordic Semiconductor nRF54H20 Radio MCU
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54H20_ENGA_CPURAD
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config NUM_IRQS
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default 471
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config NRF_REGTOOL_GENERATE_UICR
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default y
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endif # SOC_NRF54H20_ENGA_CPURAD
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@ -27,23 +27,5 @@ config SOC_NRF54H20_CPUPPR
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help
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help
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nRF54H20 CPUPPR
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nRF54H20 CPUPPR
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config SOC_NRF54H20_ENGA_CPUAPP
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bool
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select SOC_NRF54H20
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help
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nRF54H20 ENGA CPUAPP
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config SOC_NRF54H20_ENGA_CPURAD
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bool
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select SOC_NRF54H20
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help
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nRF54H20 ENGA CPURAD
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config SOC_NRF54H20_ENGA_CPUPPR
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bool
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select SOC_NRF54H20
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help
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nRF54H20 ENGA CPUPPR
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config SOC
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config SOC
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default "nrf54h20" if SOC_NRF54H20
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default "nrf54h20" if SOC_NRF54H20
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@ -44,10 +44,6 @@ static void power_domain_init(void)
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
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nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
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#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP)
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nrf_lrcconf_poweron_force_set(NRF_LRCCONF000, NRF_LRCCONF_POWER_DOMAIN_0, true);
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#endif
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}
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}
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static int trim_hsfll(void)
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static int trim_hsfll(void)
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nrf_hsfll_trim_set(hsfll, &trim);
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nrf_hsfll_trim_set(hsfll, &trim);
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nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
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nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
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#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGA_CPURAD)
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/* In this HW revision, HSFLL task frequency change needs to be
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* triggered additional time to take effect.
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*/
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nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
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#endif
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LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
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LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
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LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
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LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);
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