soc: nordic: Remove support for nRF54H20 EngA

This was a preview revision of the SoC that will no longer
be supported.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2024-03-13 17:41:37 +01:00 committed by Fabio Baltieri
commit 4d16e5b7d9
7 changed files with 0 additions and 99 deletions

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@ -1,12 +1,6 @@
# Copyright (c) 2024 Nordic Semiconductor ASA # Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CPU_PATH := $(dt_nodelabel_path,cpu)
CPU_ID := $(dt_node_reg_addr_int,$(CPU_PATH))
config RV_BOOT_HART
default $(CPU_ID) if SOC_NRF54H20_ENGA_CPUPPR
config RISCV_MCAUSE_EXCEPTION_MASK config RISCV_MCAUSE_EXCEPTION_MASK
default 0xFFF default 0xFFF

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@ -32,31 +32,6 @@ config SOC_NRF54H20_CPURAD
config SOC_NRF54H20_CPUPPR config SOC_NRF54H20_CPUPPR
depends on RISCV_CORE_NORDIC_VPR depends on RISCV_CORE_NORDIC_VPR
config SOC_NRF54H20_ENGA_CPUAPP
select ARM
select ARMV8_M_DSP
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select CPU_HAS_ARM_SAU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CPU_HAS_FPU
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
config SOC_NRF54H20_ENGA_CPURAD
select ARM
select ARMV8_M_DSP
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select CPU_HAS_ARM_SAU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CPU_HAS_FPU
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
config SOC_NRF54H20_ENGA_CPUPPR
depends on RISCV_CORE_NORDIC_VPR
if SOC_NRF54H20 if SOC_NRF54H20
config NRF_ENABLE_ICACHE config NRF_ENABLE_ICACHE

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@ -1,14 +0,0 @@
# Nordic Semiconductor nRF54H20 Application MCU
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54H20_ENGA_CPUAPP
config NUM_IRQS
default 471
config NRF_REGTOOL_GENERATE_UICR
default y
endif # SOC_NRF54H20_ENGA_CPUAPP

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@ -1,12 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54H20_ENGA_CPUPPR
config NUM_IRQS
default 496
config SYS_CLOCK_TICKS_PER_SEC
default 1000
endif # SOC_NRF54H20_ENGA_CPUPPR

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@ -1,14 +0,0 @@
# Nordic Semiconductor nRF54H20 Radio MCU
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF54H20_ENGA_CPURAD
config NUM_IRQS
default 471
config NRF_REGTOOL_GENERATE_UICR
default y
endif # SOC_NRF54H20_ENGA_CPURAD

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@ -27,23 +27,5 @@ config SOC_NRF54H20_CPUPPR
help help
nRF54H20 CPUPPR nRF54H20 CPUPPR
config SOC_NRF54H20_ENGA_CPUAPP
bool
select SOC_NRF54H20
help
nRF54H20 ENGA CPUAPP
config SOC_NRF54H20_ENGA_CPURAD
bool
select SOC_NRF54H20
help
nRF54H20 ENGA CPURAD
config SOC_NRF54H20_ENGA_CPUPPR
bool
select SOC_NRF54H20
help
nRF54H20 ENGA CPUPPR
config SOC config SOC
default "nrf54h20" if SOC_NRF54H20 default "nrf54h20" if SOC_NRF54H20

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@ -44,10 +44,6 @@ static void power_domain_init(void)
nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true); nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, true);
nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true); nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, true);
#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP)
nrf_lrcconf_poweron_force_set(NRF_LRCCONF000, NRF_LRCCONF_POWER_DOMAIN_0, true);
#endif
} }
static int trim_hsfll(void) static int trim_hsfll(void)
@ -69,12 +65,6 @@ static int trim_hsfll(void)
nrf_hsfll_trim_set(hsfll, &trim); nrf_hsfll_trim_set(hsfll, &trim);
nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE); nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
#if defined(CONFIG_SOC_NRF54H20_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54H20_ENGA_CPURAD)
/* In this HW revision, HSFLL task frequency change needs to be
* triggered additional time to take effect.
*/
nrf_hsfll_task_trigger(hsfll, NRF_HSFLL_TASK_FREQ_CHANGE);
#endif
LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP); LOG_DBG("NRF_HSFLL->TRIM.VSUP = %d", hsfll->TRIM.VSUP);
LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE); LOG_DBG("NRF_HSFLL->TRIM.COARSE = %d", hsfll->TRIM.COARSE);