diff --git a/drivers/i2c/Kconfig.stm32 b/drivers/i2c/Kconfig.stm32 index 77e36e5cf5f..1282f997abc 100644 --- a/drivers/i2c/Kconfig.stm32 +++ b/drivers/i2c/Kconfig.stm32 @@ -24,13 +24,13 @@ config I2C_STM32_V1 config I2C_STM32_V2 bool - depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32MP1X + depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32MP1X || SOC_SERIES_STM32G4X select HAS_DTS_I2C select USE_STM32_LL_I2C select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X select I2C_STM32_INTERRUPT if I2C_SLAVE help - Enable I2C support on the STM32 F0, F3, F7, L4, WBX and MP1 family of + Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1 and G4 family of processors. This driver also supports the L0 series. If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index 4764161e1a1..b2616fa87c6 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include / { @@ -166,6 +167,45 @@ label = "LPUART_1"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; + interrupts = <31 0>, <32 0>; + interrupt-names = "event", "error"; + status = "disabled"; + label= "I2C_1"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; + interrupts = <33 0>, <34 0>; + interrupt-names = "event", "error"; + status = "disabled"; + label= "I2C_2"; + }; + + i2c3: i2c@40007800 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40007800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; + interrupts = <92 0>, <93 0>; + interrupt-names = "event", "error"; + status = "disabled"; + label= "I2C_3"; + }; + }; }; diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series index 69d78837359..928c8d1b45e 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series +++ b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series @@ -28,5 +28,12 @@ config GPIO_STM32_PORTF config GPIO_STM32_PORTG default y +if I2C_STM32 + +config I2C_STM32_V2 + default y + +endif # I2C_STM32 + endif # GPIO_STM32 endif # SOC_SERIES_STM32G4X diff --git a/soc/arm/st_stm32/stm32g4/dts_fixup.h b/soc/arm/st_stm32/stm32g4/dts_fixup.h index 146a5db7b2b..a5db1a1c85f 100644 --- a/soc/arm/st_stm32/stm32g4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32g4/dts_fixup.h @@ -119,4 +119,34 @@ #define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32G4_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_ST_STM32G4_FLASH_CONTROLLER_40022000_LABEL +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY +#define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS + +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY +#define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS + +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS +#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY +#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY +#define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40007800_LABEL +#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT +#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS + /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/arm/st_stm32/stm32g4/soc.h index 09931a73c40..f7cbf7ea9aa 100644 --- a/soc/arm/st_stm32/stm32g4/soc.h +++ b/soc/arm/st_stm32/stm32g4/soc.h @@ -48,6 +48,10 @@ #include #endif /* CONFIG_SERIAL_HAS_DRIVER */ +#ifdef CONFIG_I2C +#include +#endif /* CONFIG_I2C */ + #endif /* !_ASMLANGUAGE */ #endif /* _STM32G4_SOC_H_ */