drivers: eeprom: add driver for Atmel AT24 I2C and AT25 SPI EEPROMs
Add driver for Atmel AT24 (and compatible) I2C along with Atmel AT25 (and compatible) SPI EEPROMs. Tested with: AT24LC025, AT24C256, AT25AA02E48, and AT25080. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen
Anas Nashif
parent
6e56feb2be
commit
4c9a1c59fe
3 changed files with 724 additions and 0 deletions
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@ -6,3 +6,4 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE eeprom_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_SHELL eeprom_shell.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_NATIVE_POSIX eeprom_native_posix.c)
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zephyr_library_sources_ifdef(CONFIG_EEPROM_AT2X eeprom_at2x.c)
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@ -34,4 +34,24 @@ config EEPROM_NATIVE_POSIX
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help
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Enable Native POSIX EEPROM driver.
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config EEPROM_AT2X
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bool # hidden
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help
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Enable support for Atmel AT2x (and compatible) I2C/SPI
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EEPROMs.
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config EEPROM_AT24
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bool "Atmel AT24 (and compatible) I2C EEPROM support"
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depends on (I2C && HAS_DTS_I2C)
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select EEPROM_AT2X
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help
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Enable support for Atmel AT24 (and compatible) I2C EEPROMs.
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config EEPROM_AT25
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bool "Atmel AT25 (and compatible) SPI EEPROM support"
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depends on SPI
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select EEPROM_AT2X
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help
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Enable support for Atmel AT25 (and compatible) SPI EEPROMs.
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endif # EEPROM
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703
drivers/eeprom/eeprom_at2x.c
Normal file
703
drivers/eeprom/eeprom_at2x.c
Normal file
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@ -0,0 +1,703 @@
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/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Driver for Atmel AT24 I2C and Atmel AT25 SPI EEPROMs.
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*/
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#include <drivers/eeprom.h>
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#include <drivers/gpio.h>
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#include <drivers/i2c.h>
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#include <drivers/spi.h>
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#include <sys/byteorder.h>
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#include <zephyr.h>
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#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(eeprom_at2x);
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/* AT25 instruction set */
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#define EEPROM_AT25_WRSR 0x01U /* Write STATUS register */
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#define EEPROM_AT25_WRITE 0x02U /* Write data to memory array */
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#define EEPROM_AT25_READ 0x03U /* Read data from memory array */
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#define EEPROM_AT25_WRDI 0x04U /* Reset the write enable latch */
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#define EEPROM_AT25_RDSR 0x05U /* Read STATUS register */
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#define EEPROM_AT25_WREN 0x06U /* Set the write enable latch */
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/* AT25 status register bits */
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#define EEPROM_AT25_STATUS_WIP BIT(0) /* Write-In-Process (RO) */
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#define EEPROM_AT25_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
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#define EEPROM_AT25_STATUS_BP0 BIT(2) /* Block Protection 0 (RW) */
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#define EEPROM_AT25_STATUS_BP1 BIT(3) /* Block Protection 1 (RW) */
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struct eeprom_at2x_config {
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const char *bus_dev_name;
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u16_t bus_addr;
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u32_t max_freq;
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const char *spi_cs_dev_name;
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u8_t spi_cs_pin;
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const char *wp_gpio_name;
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u32_t wp_gpio_pin;
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int wp_gpio_flags;
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size_t size;
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size_t pagesize;
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u8_t addr_width;
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bool readonly;
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u16_t timeout;
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eeprom_api_read read_fn;
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eeprom_api_write write_fn;
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};
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struct eeprom_at2x_data {
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struct device *bus_dev;
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#ifdef CONFIG_EEPROM_AT25
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struct spi_config spi_cfg;
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struct spi_cs_control spi_cs;
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#endif /* CONFIG_EEPROM_AT25 */
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struct device *wp_gpio_dev;
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struct k_mutex lock;
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};
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static inline int eeprom_at2x_write_protect(struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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u32_t value = 0;
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if (!data->wp_gpio_dev) {
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return 0;
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}
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if (config->wp_gpio_flags & GPIO_INT_ACTIVE_HIGH) {
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value = 1;
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}
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return gpio_pin_write(data->wp_gpio_dev, config->wp_gpio_pin, value);
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}
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static inline int eeprom_at2x_write_enable(struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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u32_t value = 1;
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if (!data->wp_gpio_dev) {
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return 0;
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}
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if (config->wp_gpio_flags & GPIO_INT_ACTIVE_HIGH) {
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value = 0;
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}
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return gpio_pin_write(data->wp_gpio_dev, config->wp_gpio_pin, value);
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}
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static int eeprom_at2x_read(struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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int err;
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to read past device boundary");
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return -EINVAL;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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err = config->read_fn(dev, offset, buf, len);
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k_mutex_unlock(&data->lock);
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if (err) {
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LOG_ERR("failed to read EEPROM (err %d)", err);
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return err;
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}
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return 0;
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}
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static size_t eeprom_at2x_limit_write_count(struct device *dev, off_t offset,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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size_t count = len;
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off_t page_boundary;
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/* We can at most write one page at a time */
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if (count > config->pagesize) {
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count = config->pagesize;
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}
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/* Writes can not cross a page boundary */
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page_boundary = ROUND_UP(offset + 1, config->pagesize);
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if (offset + count > page_boundary) {
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count = page_boundary - offset;
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}
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return count;
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}
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static int eeprom_at2x_write(struct device *dev, off_t offset, const void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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const u8_t *pbuf = buf;
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int ret;
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if (config->readonly) {
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LOG_WRN("attempt to write to read-only device");
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return -EACCES;
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}
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to write past device boundary");
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return -EINVAL;
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}
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k_mutex_lock(&data->lock, K_FOREVER);
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ret = eeprom_at2x_write_enable(dev);
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if (ret) {
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LOG_ERR("failed to write-enable EEPROM (err %d)", ret);
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k_mutex_unlock(&data->lock);
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return ret;
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}
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while (len) {
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ret = config->write_fn(dev, offset, pbuf, len);
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if (ret < 0) {
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LOG_ERR("failed to write to EEPROM (err %d)", ret);
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eeprom_at2x_write_protect(dev);
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k_mutex_unlock(&data->lock);
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return ret;
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}
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pbuf += ret;
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offset += ret;
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len -= ret;
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}
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ret = eeprom_at2x_write_protect(dev);
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if (ret) {
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LOG_ERR("failed to write-protect EEPROM (err %d)", ret);
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}
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k_mutex_unlock(&data->lock);
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return ret;
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}
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static size_t eeprom_at2x_size(struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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return config->size;
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}
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#ifdef CONFIG_EEPROM_AT24
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static int eeprom_at24_read(struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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s64_t timeout;
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u8_t addr[2];
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int err;
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if (config->addr_width == 16) {
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sys_put_be16(offset, addr);
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} else {
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addr[0] = offset & BIT_MASK(8);
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}
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/*
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* A write cycle may be in progress so reads must be attempted
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* until the current write cycle should be completed.
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*/
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timeout = k_uptime_get() + config->timeout;
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do {
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err = i2c_write_read(data->bus_dev, config->bus_addr,
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addr, config->addr_width / 8,
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buf, len);
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if (!err) {
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break;
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}
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k_sleep(K_MSEC(1));
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} while (timeout > k_uptime_get());
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return err;
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}
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static int eeprom_at24_write(struct device *dev, off_t offset,
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const void *buf, size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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int count = eeprom_at2x_limit_write_count(dev, offset, len);
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u8_t block[config->addr_width / 8 + count];
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s64_t timeout;
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int i = 0;
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int err;
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/*
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* Not all I2C EEPROMs support repeated start so the the
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* address (offset) and data (buf) must be provided in one
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* write transaction (block).
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*/
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if (config->addr_width == 16) {
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block[i++] = offset >> 8;
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}
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block[i++] = offset;
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memcpy(&block[i], buf, count);
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/*
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* A write cycle may already be in progress so writes must be
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* attempted until the previous write cycle should be
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* completed.
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*/
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timeout = k_uptime_get() + config->timeout;
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do {
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err = i2c_write(data->bus_dev, block, sizeof(block),
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config->bus_addr);
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if (!err) {
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break;
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}
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k_sleep(K_MSEC(1));
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} while (timeout > k_uptime_get());
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if (err < 0) {
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return err;
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}
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return count;
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}
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#endif /* CONFIG_EEPROM_AT24 */
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#ifdef CONFIG_EEPROM_AT25
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static int eeprom_at25_rdsr(struct device *dev, u8_t *status)
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{
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struct eeprom_at2x_data *data = dev->driver_data;
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u8_t rdsr[2] = { EEPROM_AT25_RDSR, 0 };
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u8_t sr[2];
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int err;
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const struct spi_buf tx_buf = {
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.buf = rdsr,
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.len = sizeof(rdsr),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_buf = {
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.buf = sr,
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.len = sizeof(sr),
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};
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const struct spi_buf_set rx = {
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.buffers = &rx_buf,
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.count = 1,
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};
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err = spi_transceive(data->bus_dev, &data->spi_cfg, &tx, &rx);
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if (!err) {
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*status = sr[1];
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}
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return err;
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}
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static int eeprom_at25_wait_for_idle(struct device *dev)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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s64_t timeout;
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u8_t status;
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int err;
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timeout = k_uptime_get() + config->timeout;
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do {
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err = eeprom_at25_rdsr(dev, &status);
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if (err) {
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LOG_ERR("Could not read status register (err %d)", err);
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return err;
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}
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if (!(status & EEPROM_AT25_STATUS_WIP)) {
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return 0;
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}
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k_sleep(K_MSEC(1));
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} while (timeout > k_uptime_get());
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return -EBUSY;
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}
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static int eeprom_at25_read(struct device *dev, off_t offset, void *buf,
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size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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size_t cmd_len = 1 + config->addr_width / 8;
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u8_t cmd[4] = { EEPROM_AT25_READ, 0, 0, 0 };
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u8_t *paddr;
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int err;
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const struct spi_buf tx_buf = {
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.buf = cmd,
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.len = cmd_len,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_bufs[2] = {
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{
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.buf = NULL,
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.len = cmd_len,
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},
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{
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.buf = buf,
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.len = len,
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},
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};
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const struct spi_buf_set rx = {
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.buffers = rx_bufs,
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.count = ARRAY_SIZE(rx_bufs),
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};
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if (!len) {
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return 0;
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}
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if ((offset + len) > config->size) {
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LOG_WRN("attempt to read past device boundary");
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return -EINVAL;
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}
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paddr = &cmd[1];
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switch (config->addr_width) {
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case 24:
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*paddr++ = offset >> 16;
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/* Fallthrough */
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case 16:
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*paddr++ = offset >> 8;
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/* Fallthrough */
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case 8:
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*paddr++ = offset;
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break;
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default:
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__ASSERT(0, "invalid address width");
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}
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err = eeprom_at25_wait_for_idle(dev);
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if (err) {
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LOG_ERR("EEPROM idle wait failed (err %d)", err);
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k_mutex_unlock(&data->lock);
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return err;
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}
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return spi_transceive(data->bus_dev, &data->spi_cfg, &tx, &rx);
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}
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static int eeprom_at25_wren(struct device *dev)
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{
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struct eeprom_at2x_data *data = dev->driver_data;
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u8_t cmd = EEPROM_AT25_WREN;
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const struct spi_buf tx_buf = {
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.buf = &cmd,
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.len = 1,
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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return spi_write(data->bus_dev, &data->spi_cfg, &tx);
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}
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static int eeprom_at25_write(struct device *dev, off_t offset,
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const void *buf, size_t len)
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{
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const struct eeprom_at2x_config *config = dev->config->config_info;
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struct eeprom_at2x_data *data = dev->driver_data;
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int count = eeprom_at2x_limit_write_count(dev, offset, len);
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u8_t cmd[4] = { EEPROM_AT25_WRITE, 0, 0, 0 };
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size_t cmd_len = 1 + config->addr_width / 8;
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u8_t *paddr;
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int err;
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const struct spi_buf tx_bufs[2] = {
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{
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.buf = cmd,
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.len = cmd_len,
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},
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{
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.buf = (void *)buf,
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.len = count,
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},
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};
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const struct spi_buf_set tx = {
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.buffers = tx_bufs,
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.count = ARRAY_SIZE(tx_bufs),
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};
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paddr = &cmd[1];
|
||||
switch (config->addr_width) {
|
||||
case 24:
|
||||
*paddr++ = offset >> 16;
|
||||
/* Fallthrough */
|
||||
case 16:
|
||||
*paddr++ = offset >> 8;
|
||||
/* Fallthrough */
|
||||
case 8:
|
||||
*paddr++ = offset;
|
||||
break;
|
||||
default:
|
||||
__ASSERT(0, "invalid address width");
|
||||
}
|
||||
|
||||
err = eeprom_at25_wait_for_idle(dev);
|
||||
if (err) {
|
||||
LOG_ERR("EEPROM idle wait failed (err %d)", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = eeprom_at25_wren(dev);
|
||||
if (err) {
|
||||
LOG_ERR("failed to disable write protection (err %d)", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = spi_transceive(data->bus_dev, &data->spi_cfg, &tx, NULL);
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
#endif /* CONFIG_EEPROM_AT25 */
|
||||
|
||||
static int eeprom_at2x_init(struct device *dev)
|
||||
{
|
||||
const struct eeprom_at2x_config *config = dev->config->config_info;
|
||||
struct eeprom_at2x_data *data = dev->driver_data;
|
||||
int err;
|
||||
|
||||
k_mutex_init(&data->lock);
|
||||
|
||||
data->bus_dev = device_get_binding(config->bus_dev_name);
|
||||
if (!data->bus_dev) {
|
||||
LOG_ERR("could not get parent bus device");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_EEPROM_AT25
|
||||
data->spi_cfg.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB |
|
||||
SPI_WORD_SET(8);
|
||||
data->spi_cfg.frequency = config->max_freq;
|
||||
data->spi_cfg.slave = config->bus_addr;
|
||||
|
||||
if (config->spi_cs_dev_name) {
|
||||
data->spi_cs.gpio_dev =
|
||||
device_get_binding(config->spi_cs_dev_name);
|
||||
if (!data->spi_cs.gpio_dev) {
|
||||
LOG_ERR("could not get SPI CS GPIO device");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data->spi_cs.gpio_pin = config->spi_cs_pin;
|
||||
data->spi_cfg.cs = &data->spi_cs;
|
||||
}
|
||||
#endif /* CONFIG_EEPROM_AT25 */
|
||||
|
||||
if (config->wp_gpio_name) {
|
||||
data->wp_gpio_dev = device_get_binding(config->wp_gpio_name);
|
||||
if (!data->wp_gpio_dev) {
|
||||
LOG_ERR("could not get WP GPIO device");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = gpio_pin_configure(data->wp_gpio_dev, config->wp_gpio_pin,
|
||||
GPIO_DIR_OUT | config->wp_gpio_flags);
|
||||
if (err) {
|
||||
LOG_ERR("failed to configure WP GPIO pin (err %d)",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = eeprom_at2x_write_protect(dev);
|
||||
if (err) {
|
||||
LOG_ERR("failed to write-protect EEPROM (err %d)", err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct eeprom_driver_api eeprom_at2x_api = {
|
||||
.read = eeprom_at2x_read,
|
||||
.write = eeprom_at2x_write,
|
||||
.size = eeprom_at2x_size,
|
||||
};
|
||||
|
||||
#define ASSERT_AT24_ADDR_W_VALID(w) \
|
||||
BUILD_ASSERT_MSG(w == 8U || w == 16U, \
|
||||
"Unsupported address width")
|
||||
|
||||
#define ASSERT_AT25_ADDR_W_VALID(w) \
|
||||
BUILD_ASSERT_MSG(w == 8U || w == 16U || w == 24U, \
|
||||
"Unsupported address width")
|
||||
|
||||
#define ASSERT_PAGESIZE_IS_POWER_OF_2(page) \
|
||||
BUILD_ASSERT_MSG((page != 0U) && ((page & (page - 1)) == 0U), \
|
||||
"Page size is not a power of two")
|
||||
|
||||
#define ASSERT_SIZE_PAGESIZE_VALID(size, page) \
|
||||
BUILD_ASSERT_MSG(size % page == 0U, \
|
||||
"Size is not an integer multiple of page size")
|
||||
|
||||
#define EEPROM_AT2X_DEVICE(t, n) \
|
||||
ASSERT_PAGESIZE_IS_POWER_OF_2(DT_INST_##n##_ATMEL_AT##t##_PAGESIZE); \
|
||||
ASSERT_SIZE_PAGESIZE_VALID(DT_INST_##n##_ATMEL_AT##t##_SIZE, \
|
||||
DT_INST_##n##_ATMEL_AT##t##_PAGESIZE); \
|
||||
ASSERT_AT##t##_ADDR_W_VALID(DT_INST_##n##_ATMEL_AT##t##_ADDRESS_WIDTH);\
|
||||
static const struct eeprom_at2x_config eeprom_at##t##_config_##n = { \
|
||||
.bus_dev_name = DT_INST_##n##_ATMEL_AT##t##_BUS_NAME, \
|
||||
.bus_addr = DT_INST_##n##_ATMEL_AT##t##_BASE_ADDRESS, \
|
||||
.max_freq = DT_INST_##n##_ATMEL_AT##t##_SPI_MAX_FREQUENCY, \
|
||||
.spi_cs_dev_name = \
|
||||
DT_INST_##n##_ATMEL_AT##t##_CS_GPIOS_CONTROLLER, \
|
||||
.spi_cs_pin = DT_INST_##n##_ATMEL_AT##t##_CS_GPIOS_PIN, \
|
||||
.wp_gpio_name = \
|
||||
DT_INST_##n##_ATMEL_AT##t##_WP_GPIOS_CONTROLLER, \
|
||||
.wp_gpio_pin = DT_INST_##n##_ATMEL_AT##t##_WP_GPIOS_PIN, \
|
||||
.wp_gpio_flags = DT_INST_##n##_ATMEL_AT##t##_WP_GPIOS_FLAGS, \
|
||||
.size = DT_INST_##n##_ATMEL_AT##t##_SIZE, \
|
||||
.pagesize = DT_INST_##n##_ATMEL_AT##t##_PAGESIZE, \
|
||||
.addr_width = DT_INST_##n##_ATMEL_AT##t##_ADDRESS_WIDTH, \
|
||||
.readonly = DT_INST_##n##_ATMEL_AT##t##_READ_ONLY, \
|
||||
.timeout = DT_INST_##n##_ATMEL_AT##t##_TIMEOUT, \
|
||||
.read_fn = eeprom_at##t##_read, \
|
||||
.write_fn = eeprom_at##t##_write, \
|
||||
}; \
|
||||
static struct eeprom_at2x_data eeprom_at##t##_data_##n; \
|
||||
DEVICE_AND_API_INIT(eeprom_at##t##_##n, \
|
||||
DT_INST_##n##_ATMEL_AT##t##_LABEL, \
|
||||
&eeprom_at2x_init, &eeprom_at##t##_data_##n, \
|
||||
&eeprom_at##t##_config_##n, POST_KERNEL, \
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
||||
&eeprom_at2x_api)
|
||||
|
||||
#ifdef CONFIG_EEPROM_AT24
|
||||
#if DT_INST_0_ATMEL_AT24
|
||||
#define DT_INST_0_ATMEL_AT24_SPI_MAX_FREQUENCY 0
|
||||
#define DT_INST_0_ATMEL_AT24_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_0_ATMEL_AT24_CS_GPIOS_PIN 0
|
||||
#ifndef DT_INST_0_ATMEL_AT24_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_0_ATMEL_AT24_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_0_ATMEL_AT24_WP_GPIOS_PIN 0
|
||||
#define DT_INST_0_ATMEL_AT24_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(24, 0);
|
||||
#endif
|
||||
|
||||
#if DT_INST_1_ATMEL_AT24
|
||||
#define DT_INST_1_ATMEL_AT24_SPI_MAX_FREQUENCY 0
|
||||
#define DT_INST_1_ATMEL_AT24_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_1_ATMEL_AT24_CS_GPIOS_PIN 0
|
||||
#ifndef DT_INST_1_ATMEL_AT24_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_1_ATMEL_AT24_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_1_ATMEL_AT24_WP_GPIOS_PIN 0
|
||||
#define DT_INST_1_ATMEL_AT24_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(24, 1);
|
||||
#endif
|
||||
|
||||
#if DT_INST_2_ATMEL_AT24
|
||||
#define DT_INST_2_ATMEL_AT24_SPI_MAX_FREQUENCY 0
|
||||
#define DT_INST_2_ATMEL_AT24_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_2_ATMEL_AT24_CS_GPIOS_PIN 0
|
||||
#ifndef DT_INST_2_ATMEL_AT24_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_2_ATMEL_AT24_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_2_ATMEL_AT24_WP_GPIOS_PIN 0
|
||||
#define DT_INST_2_ATMEL_AT24_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(24, 2);
|
||||
#endif
|
||||
|
||||
#if DT_INST_3_ATMEL_AT24
|
||||
#define DT_INST_3_ATMEL_AT24_SPI_MAX_FREQUENCY 0
|
||||
#define DT_INST_3_ATMEL_AT24_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_3_ATMEL_AT24_CS_GPIOS_PIN 0
|
||||
#ifndef DT_INST_3_ATMEL_AT24_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_3_ATMEL_AT24_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_3_ATMEL_AT24_WP_GPIOS_PIN 0
|
||||
#define DT_INST_3_ATMEL_AT24_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(24, 3);
|
||||
#endif
|
||||
#endif /* CONFIG_EEPROM_AT24 */
|
||||
|
||||
#ifdef CONFIG_EEPROM_AT25
|
||||
#if DT_INST_0_ATMEL_AT25
|
||||
#ifndef DT_INST_0_ATMEL_AT25_CS_GPIOS_CONTROLLER
|
||||
#define DT_INST_0_ATMEL_AT25_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_0_ATMEL_AT25_CS_GPIOS_PIN 0
|
||||
#endif
|
||||
#ifndef DT_INST_0_ATMEL_AT25_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_0_ATMEL_AT25_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_0_ATMEL_AT25_WP_GPIOS_PIN 0
|
||||
#define DT_INST_0_ATMEL_AT25_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(25, 0);
|
||||
#endif
|
||||
|
||||
#if DT_INST_1_ATMEL_AT25
|
||||
#ifndef DT_INST_1_ATMEL_AT25_CS_GPIOS_CONTROLLER
|
||||
#define DT_INST_1_ATMEL_AT25_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_1_ATMEL_AT25_CS_GPIOS_PIN 0
|
||||
#endif
|
||||
#ifndef DT_INST_1_ATMEL_AT25_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_1_ATMEL_AT25_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_1_ATMEL_AT25_WP_GPIOS_PIN 0
|
||||
#define DT_INST_1_ATMEL_AT25_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(25, 1);
|
||||
#endif
|
||||
|
||||
#if DT_INST_2_ATMEL_AT25
|
||||
#ifndef DT_INST_2_ATMEL_AT25_CS_GPIOS_CONTROLLER
|
||||
#define DT_INST_2_ATMEL_AT25_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_2_ATMEL_AT25_CS_GPIOS_PIN 0
|
||||
#endif
|
||||
#ifndef DT_INST_2_ATMEL_AT25_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_2_ATMEL_AT25_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_2_ATMEL_AT25_WP_GPIOS_PIN 0
|
||||
#define DT_INST_2_ATMEL_AT25_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(25, 2);
|
||||
#endif
|
||||
|
||||
#if DT_INST_3_ATMEL_AT25
|
||||
#ifndef DT_INST_3_ATMEL_AT25_CS_GPIOS_CONTROLLER
|
||||
#define DT_INST_3_ATMEL_AT25_CS_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_3_ATMEL_AT25_CS_GPIOS_PIN 0
|
||||
#endif
|
||||
#ifndef DT_INST_3_ATMEL_AT25_WP_GPIOS_CONTROLLER
|
||||
#define DT_INST_3_ATMEL_AT25_WP_GPIOS_CONTROLLER NULL
|
||||
#define DT_INST_3_ATMEL_AT25_WP_GPIOS_PIN 0
|
||||
#define DT_INST_3_ATMEL_AT25_WP_GPIOS_FLAGS 0
|
||||
#endif
|
||||
EEPROM_AT2X_DEVICE(25, 3);
|
||||
#endif
|
||||
#endif /* CONFIG_EEPROM_AT25 */
|
||||
Loading…
Add table
Add a link
Reference in a new issue