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boards: nucleo_l412rb_p: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-04-30 09:25:18 +02:00 • committed by Maureen Helm
commit 4c7585e693
2 changed files with 22 additions and 15 deletions
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21
boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts
View file

@ -42,6 +42,27 @@
};
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <10>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
current-speed = <115200>;

16
boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig
View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32L4X=y
CONFIG_SOC_STM32L412XX=y
# 80MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -24,17 +22,5 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# PLL configuration
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# produce 80MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=10
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1