x86: prefix x86 SSBD and IBRS related kconfigs with X86
There are two kconfigs that are security related and are x86 specific. Prefix them with X86 to put them under the x86 namespace. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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3 changed files with 30 additions and 6 deletions
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@ -397,7 +397,7 @@ config X86_NO_SPECULATIVE_VULNERABILITIES
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or is a newer chip which is immune to the class of vulnerabilities
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or is a newer chip which is immune to the class of vulnerabilities
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which exploit speculative execution side channel attacks.
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which exploit speculative execution side channel attacks.
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config DISABLE_SSBD
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config X86_DISABLE_SSBD
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bool "Disable Speculative Store Bypass"
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bool "Disable Speculative Store Bypass"
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depends on USERSPACE
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V4
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default y if !X86_NO_SPECTRE_V4
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@ -417,7 +417,16 @@ config DISABLE_SSBD
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Even if enabled, will have no effect on CPUs that do not
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Even if enabled, will have no effect on CPUs that do not
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require this feature.
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require this feature.
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config ENABLE_EXTENDED_IBRS
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config DISABLE_SSBD
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bool "Disable Speculative Store Bypass [DEPRECATED]"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V4
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select X86_DISABLE_SSBD
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select DEPRECATED
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help
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Deprecated. Use CONFIG_X86_DISABLE_SSBD instead.
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config X86_ENABLE_EXTENDED_IBRS
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bool "Extended IBRS"
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bool "Extended IBRS"
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depends on USERSPACE
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V2
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default y if !X86_NO_SPECTRE_V2
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@ -426,6 +435,15 @@ config ENABLE_EXTENDED_IBRS
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Speculation 'always on' feature. This mitigates Indirect Branch
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Speculation 'always on' feature. This mitigates Indirect Branch
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Control vulnerabilities (aka Spectre V2).
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Control vulnerabilities (aka Spectre V2).
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config ENABLE_EXTENDED_IBRS
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bool "Extended IBRS [DEPRECATED]"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V2
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select X86_ENABLE_EXTENDED_IBRS
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select DEPRECATED
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help
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Deprecated. Use CONFIG_X86_ENABLE_EXTENDED_IBRS instead.
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config X86_BOUNDS_CHECK_BYPASS_MITIGATION
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config X86_BOUNDS_CHECK_BYPASS_MITIGATION
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bool
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bool
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depends on USERSPACE
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depends on USERSPACE
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@ -16,19 +16,19 @@
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* https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
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* https://software.intel.com/security-software-guidance/api-app/sites/default/files/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
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*/
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*/
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#if defined(CONFIG_DISABLE_SSBD) || defined(CONFIG_ENABLE_EXTENDED_IBRS)
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#if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS)
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static int spec_ctrl_init(void)
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static int spec_ctrl_init(void)
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{
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{
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uint32_t enable_bits = 0U;
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uint32_t enable_bits = 0U;
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uint32_t cpuid7 = z_x86_cpuid_extended_features();
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uint32_t cpuid7 = z_x86_cpuid_extended_features();
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#ifdef CONFIG_DISABLE_SSBD
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#ifdef CONFIG_X86_DISABLE_SSBD
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if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) {
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if ((cpuid7 & CPUID_SPEC_CTRL_SSBD) != 0U) {
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enable_bits |= X86_SPEC_CTRL_MSR_SSBD;
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enable_bits |= X86_SPEC_CTRL_MSR_SSBD;
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}
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}
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#endif
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#endif
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#ifdef CONFIG_ENABLE_EXTENDED_IBRS
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#ifdef CONFIG_X86_ENABLE_EXTENDED_IBRS
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if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) {
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if ((cpuid7 & CPUID_SPEC_CTRL_IBRS) != 0U) {
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enable_bits |= X86_SPEC_CTRL_MSR_IBRS;
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enable_bits |= X86_SPEC_CTRL_MSR_IBRS;
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}
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}
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@ -44,4 +44,4 @@ static int spec_ctrl_init(void)
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}
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}
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SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0);
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SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0);
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#endif /* CONFIG_DISABLE_SSBD || CONFIG_ENABLE_EXTENDED_IBRS */
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#endif /* CONFIG_X86_DISABLE_SSBD || CONFIG_X86_ENABLE_EXTENDED_IBRS */
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@ -142,5 +142,11 @@ Userspace
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Architectures
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Architectures
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*************
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*************
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* x86
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* Kconfigs ``CONFIG_DISABLE_SSBD`` and ``CONFIG_ENABLE_EXTENDED_IBRS``
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are deprecated. Use :kconfig:option:`CONFIG_X86_DISABLE_SSBD` and
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:kconfig:option:`CONFIG_X86_ENABLE_EXTENDED_IBRS` instead.
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Xtensa
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Xtensa
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======
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======
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