From 4be438254a51e230e929055504fc4871a96f478d Mon Sep 17 00:00:00 2001 From: Khor Swee Aun Date: Fri, 3 Feb 2023 15:16:04 +0800 Subject: [PATCH] codeowners: Add code owner for INTEL FPGA NIOSV Add code owner for INTEL FPGA NIOSV dts, SoC and board. Signed-off-by: Khor Swee Aun --- CODEOWNERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CODEOWNERS b/CODEOWNERS index 1686a7fb64c..067003ba651 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -81,6 +81,7 @@ /soc/riscv/riscv-privilege/andes_v5/ @cwshu @kevinwang821020 @jimmyzhe /soc/riscv/riscv-privilege/neorv32/ @henrikbrixandersen /soc/riscv/riscv-privilege/gd32vf103/ @soburi +/soc/riscv/riscv-privilege/niosv/ @sweeaun /soc/x86/ @dcpleung @nashif @jenmwms @aasthagr /arch/xtensa/ @dcpleung @andyross @nashif /soc/xtensa/ @dcpleung @andyross @nashif @@ -173,6 +174,7 @@ /boards/riscv/adp_xc7k_ae350/ @cwshu @kevinwang821020 @jimmyzhe /boards/riscv/longan_nano/ @soburi /boards/riscv/neorv32/ @henrikbrixandersen +/boards/riscv/niosv_m/ @sweeaun /boards/shields/ @erwango /boards/shields/atmel_rf2xx/ @nandojve /boards/shields/esp_8266/ @nandojve @@ -510,6 +512,7 @@ /dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/riscv/starfive/ @rajnesh-kanwal /dts/riscv/andes/andes_v5* @cwshu @kevinwang821020 @jimmyzhe +/dts/riscv/niosv/niosv-m.dtsi @sweeaun /dts/arm/armv*m.dtsi @galak @ioannisg /dts/arm/armv7-a.dtsi @ibirnbaum /dts/arm/armv7-r.dtsi @bbolen @stephanosio @@ -550,6 +553,7 @@ /dts/bindings/sensor/*bme680* @BoschSensortec /dts/bindings/sensor/*ina23* @bbilas /dts/bindings/sensor/st* @avisconti +/dts/bindings/cpu/intel,niosv.yaml @sweeaun /dts/common/ @galak /include/ @nashif @carlescufi @galak @MaureenHelm /include/zephyr/drivers/*/*litex* @mateusz-holenko @kgugala @pgielda